Device Structure Optimization of MOS Transistors for Reduction of Low Frequency Noise

采用可对100多万个晶体管的噪声进行统计分析的测量方法，对不同器件参数的MOS晶体管的噪声特性进行了评估。结果表明，与标准表面沟道结构相比，埋层宽度为60 nm的埋沟道结构中随机电报噪声的出现概率降低到1/60。通过引入埋沟结构的降噪机理进行了阐明。为实现超高灵敏度CMOS图像传感器，提出了低噪声MOS晶体管的器件结构优化方法。

The noise characteristics of MOS transistors with various device parameters were evaluated using the measurement method that can statistically analyze noise of more than one million transistors. It was confirmed that the appearance probability of random telegraph noise in buried channel structure with buried layer width of 60nm is reduced to 1/60 compared to the standard surface channel structure. The noise reduction mechanism by an introduction of the buried channel structure was clarified. The device structure optimization methodology for low noise MOS transistor was proposed for the realization of very high sensitivity CMOS image sensors.