Advanced thermoelectric properties in 1D quantum-confined core-shell nanowire heterostructures

该提议旨在建立核-壳半导体纳米线异质结构，作为先进的纳米热电材料的实验平台，利用核-壳结构的量子限制介导的载流子输运和声子性质的几个优点。在申请人取得的第一批有希望的进展的基础上，该项目的重点是探索新型的基于III-V的核壳纳米线，这些纳米线同时提供高载流子迁移率、强一维限制和长的准弹道式平均载流子自由程，以及大的原子质量对比和限制热传输的结构特征。将特别关注迄今未被探索的InAs-AlAsSb核壳纳米线作为一种新的高迁移率晶格匹配的1Dn沟道，其中将评估控制1D传输的关键因素，并强调与1D子带结构相关的热电势的增强。相关的热输运光谱将被用来评估通过尺寸效应、合金化和核壳结构中的多壳层界面来调节声子散射而最小化的晶格热导率。由于未来的功能纳米热电同时需要n沟道和p沟道器件，我们还将把为n型InAs-AlAsSb沟道开发的方法应用于高迁移率的p型GaSb-AlAsSb沟道。在高迁移率n-InAs和p-GaSb沟道方面的共同努力将进一步为双极纳米热电材料以及未来硅基CMOS逻辑电路中的共集成方案奠定重要基础。

This proposal aims to establish core-shell semiconductor nanowire heterostructures as an experimental platform for advanced nano-thermoelectric materials that exploit several advantages of quantum confinement mediated carrier transport and phonon properties tailored by the core-shell structure. Based on first promising advances made by the applicant, the focus of this project is to explore new types of III-V based core-shell nanowires that simultaneously offer high carrier mobility, strong 1D-confinement with long quasi-ballistic mean free paths of carriers, as well as large atomic mass contrast and structural features that limit thermal transport. Particular attention will be directed towards hitherto unexplored InAs-AlAsSb core-shell nanowires as a new high-mobility lattice-matched 1D n-channel, where key factors governing 1D-transport will be evaluated and enhancements in thermopower related to the 1D-subband structure highlighted. Correlated thermal transport spectroscopy will be performed to evaluate the lattice thermal conductivity minimized by tuning phonon scattering via size effects, alloying and multi-shell interfaces in the core-shell structure. As future functional nano-thermoelectrics require both n- and p-channel devices, we will also apply the methodologies developed for n-type InAs-AlAsSb channels to high-mobility p-type GaSb-AlAsSb channels. The combined efforts on high-mobility n-InAs and p-GaSb channels will further lay important grounds for ambipolar nano-thermoelectrics as well as for future co-integration schemes in Si-based CMOS logic circuits.