Development of a Energy-Recovering Low-Power Processor Architecture.
Development of a Energy-Recovering Low-Power Processor Architecture.
批准号:
11558035
负责人:
MOSHNYAGA Vasily
金额:
$5.06万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
1999
资助国家:
日本
项目状态:
已结题
起止时间:
1999 至 2001
中文摘要
(A)能量回收处理器体系结构的开发及其原型芯片实现。我们研究了能量回收处理器体系结构的新概念,并给出了其实现技术。由于绝热电荷回收和指令和数据的重用,该结构与传统的处理器设计相比,功耗降低了近两个数量级。为了评估该体系结构,设计并制作了一个原型LSI芯片。(B)开发了减少处理硬件转换活跃度的体系结构技术。提出了几种通过数据驱动操作数编码、自适应位宽压缩、操作数变换、旁路等方法来最小化功能单元和寄存器堆的切换活跃度的新方案。与传统技术不同,这些方法可以动态地禁用其值保持不变的硬件位,从而在不影响处理精度的情况下减少不必要的信号变化。该方案简单易行。(C)系统存储器可变电压降低体系结构技术的发展。已经提出了用于在指令发布队列、数据和指令高速缓存中自适应降低电压的新电路技术。与现有的设计方法相比,该方法动态地将电源电压调整到指令并行度(发布队列)以及访问(高速缓存)的局部性,在不影响性能和非常小的面积开销的情况下将这些单元中的能量消耗减少到原来的1/2。
英文摘要
(a) Development of a Energy-Recovering Processor Architecture and its prototype chip implementation. We investigated a new concept of Energy-Recovering Processor Architecture and presented techniques for its implementation. Due to adiabatic charge-recovering and instruction and, data reuse, the architecture lowers the energy consumption by almost two orders of magnitude in comparison to the traditional processor design. To evaluate the architecture, a prototype LSI chip have been designed and fabricated.(b) Development of Architectural Techniques for Reducing Transition Activity of Processing Hardware.Several new schemes to minimize switching activity of functional units, and register files by datadriven operand encoding, adaptive bit-width compression, operand transformation, bypassing, etc. have been proposed. Unlike conventional techniques, these methods can dynamically disable the hardware bits whose values remain unchanged, thus reducing unnecessary signal variations as much as ha]f without affecting the processing accuracy. The schemes are simple and easy in implementation.(c) Development of Architectural Techniques for Variable Voltage Reduction of System Memory. New circuit techniques for adaptive voltage reduction in instruction issue queue, data and instruction caches have been proposed. In contrast to existing design approaches, the methods dynamically adjust the supply voltage to the level of instruction parallelism (issue queue) as well as the locality of accesses (caches), reducing the energy dissipation in these units by a factor of two without any impact on performance and very small area overhead.
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V. Moshnyaga: "Techniques for Bit-Width Truncation in Video Processing Hardware"Proceedings of Int. Workshop on Power, Timing Optimization and Simulation of Integrated Circuits. 240-248 (1999)
V. Moshnyaga:“视频处理硬件中的位宽截断技术”国际会议录。
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V.G.Moshnyaga: "Reducing Switching Activity of Subtraction via Variable Truncation of the Most Significant Bits"Journal of VLSI Signal Processing Systems. (accepted for publication). (2002)
V.G.Moshnyaga:“通过最高有效位的可变截断来减少减法的切换活动”VLSI 信号处理系统杂志。
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V.G.Moshnyaga: "Reducing switching activity of subtraction via bit truncation"IEEE International Conference on Circuits and Systems(SCS'2001). 165-168 (2001)
V.G.Moshnyaga:“通过位截断减少减法的切换活动”IEEE 国际电路与系统会议(SCS2001)。
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井上弘士, モシニャガワシリー, 村上和彰: "実行頻度の偏りを利用した命令ROMの低消費エネルギー化手法"第15回 回路とシステム(軽井沢)ワークショップ. (2002)
Hiroshi Inoue、Vasily Moshinyaga、Kazuaki Murakami:“使用执行频率偏差的指令 ROM 的低能耗方法”第 15 届电路与系统(轻井泽)研讨会(2002 年)。
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V. Moshnyaga: "lleducing Switching Activity of Subtraction via Variable Truncation of the Most Significant Bits"accepted for publication in Journal of VLSI Signal Processing. (2002)
V. Moshnyaga:“lleducing Switching Activity of Subtraction via Variable Truncation of the Most Significant Bits”被接受发表在《VLSI 信号处理杂志》上。
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共 42 条
低消費電力VLSI乗算器の構成法に関する研究
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批准号:07780255
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项目类别:Grant-in-Aid for Encouragement of Young Scientists (A)
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资助金额:$0.58万
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财政年份:1995
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负责人:MOSHNYAGA Vasily
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依托单位:
構成要素の詳細情報に基づく大規模集積回路の高位合成に関する研究
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批准号:06780255
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项目类别:Grant-in-Aid for Encouragement of Young Scientists (A)
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资助金额:$0.64万
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财政年份:1994
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负责人:MOSHNYAGA Vasily
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依托单位:
海外基金