Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing

由于互连的复杂性，存储器和逻辑模块之间的通信瓶颈是当前深亚微米级超大规模集成电路片上系统中最严重的问题之一。在这种情况下，有望开发出适用于千兆赫时钟操作的高性能、低功耗VLSI电路技术。在这项研究中，我们提出了多值VLSI利用差分对电路，具有高驱动能力和铁电电容逻辑的低功耗逻辑存储器VLSI。针对高速低功耗VLSI系统，提出了一种基于多值信号的高性能多值VLSIA新型源耦合逻辑方式。所有的差分对电路都由双轨信号驱动，我们称之为“全源耦合逻辑”。设计和实现结果表明，该全源耦合逻辑电路的性能明显优于传统的多值源耦合逻辑电路。它是一种适用于多千兆赫低频工作的电路技术。针对无通信瓶颈的超大规模集成电路系统，提出了一种功能通栅极和非易失性内存逻辑结构。残余极化电荷的跃迁和铁电电容器的电容耦合使得存储和开关功能合并到铁电电容器中。使用基于铁电的非易失性存储器可以切断泄漏电流。与采用0.6μm铁电/CMOS工艺的等效CMOS电路相比，将铁电电路应用于CAM实现中，动态功耗降低约一半，静态功耗降低1/22000。

The communication bottleneck between memories and logic modules is one of the most serious problems due to interconnection complexity in recent deep-submicron VLSI systems-on-a-chip. In the situation, high-performance and low-power VLSI circuit technologies suitable for multi-giga-hertz clock operations are expected to be developed. In this study, we proposed multiple-valued VLSI utilizing differential-pair circuit which has high-driving capability and ferroelectric-capacitor logic for low-power logic-in-memory VLSI.1.Development of the highest performance multiple-valued VLSIA novel-source-coupled logic style using multiple-valued signals is proposed for high-speed-low-power VLSI system. All the differential-pair circuits are driven by dual-rail signals, which we call "full source-coupled logic". Design and implementation results show that the performance of the full-source coupled logic circuit is very superior to the conventional multiple-valued source-coupled logic circuit. It is a useful circuit technology for multi-gigahertz and low-voltage operations.2.Ferroelectic Logic-in-Memory ArchitectureA functional pass gate and a nonvolatile logic-in-memory architecture are proposed for communication-bottleneck-free VLSI system. Transition of a remnant-polarization charge and capacitive coupling of a ferroelectric capacitor makes storage and switching functions which are merged into a ferroelectric capacitor. The use of ferroelectric-based non-volatile storage makes leakage currents cut off. Applying the ferroelectric based circuitry to CAM implementation results in about half dynamic power reduction and 1/22000 static power reduction in comparison with the equivalent CMOS implementation under 0.6μm ferroelecric/CMOS process.