Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing

基于双轨多值数字计算的无互连超大规模集成电路系统

• 批准号: 12480064
• 负责人: KAMEYAMA MICHITAKA
• 金额: $ 5.06万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2000
• 资助国家: 日本
• 起止时间: 2000 至 2002
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-12480064/
• 关键词: Dual-Rail Current-Mode Multiple-Valued Integrated Circuit; Logic-In-Memory VLSI; Source-Coupled Logic; Fine-Grain Pipelinign; Ferro-Electric Device; Nonvolatile Logic-in-Mmemory; 電圧・電流ハイブリッドモード多値集積回路; ドミノ理論; パストランジスタ理論; ソース結合形理論; 多値VLSIプロセッサ; パ

The communication bottleneck between memories and logic modules is one of the most serious problems due to interconnection complexity in recent deep-submicron VLSI systems-on-a-chip. In the situation, high-performance and low-power VLSI circuit technologies suitable for multi-giga-hertz clock operations are expected to be developed. In this study, we proposed multiple-valued VLSI utilizing differential-pair circuit which has high-driving capability and ferroelectric-capacitor logic for low-power logic-in-memory VLSI.1.Development of the highest performance multiple-valued VLSIA novel-source-coupled logic style using multiple-valued signals is proposed for high-speed-low-power VLSI system. All the differential-pair circuits are driven by dual-rail signals, which we call "full source-coupled logic". Design and implementation results show that the performance of the full-source coupled logic circuit is very superior to the conventional multiple-valued source-coupled logic circuit. It is a useful circuit technology for multi-gigahertz and low-voltage operations.2.Ferroelectic Logic-in-Memory ArchitectureA functional pass gate and a nonvolatile logic-in-memory architecture are proposed for communication-bottleneck-free VLSI system. Transition of a remnant-polarization charge and capacitive coupling of a ferroelectric capacitor makes storage and switching functions which are merged into a ferroelectric capacitor. The use of ferroelectric-based non-volatile storage makes leakage currents cut off. Applying the ferroelectric based circuitry to CAM implementation results in about half dynamic power reduction and 1/22000 static power reduction in comparison with the equivalent CMOS implementation under 0.6μm ferroelecric/CMOS process.

由于互连的复杂性，存储器和逻辑模块之间的通信瓶颈是当前深亚微米级超大规模集成电路片上系统中最严重的问题之一。在这种情况下，有望开发出适用于千兆赫时钟操作的高性能、低功耗VLSI电路技术。在这项研究中，我们提出了多值VLSI利用差分对电路，具有高驱动能力和铁电电容逻辑的低功耗逻辑存储器VLSI。针对高速低功耗VLSI系统，提出了一种基于多值信号的高性能多值VLSIA新型源耦合逻辑方式。所有的差分对电路都由双轨信号驱动，我们称之为“全源耦合逻辑”。设计和实现结果表明，该全源耦合逻辑电路的性能明显优于传统的多值源耦合逻辑电路。它是一种适用于多千兆赫低频工作的电路技术。针对无通信瓶颈的超大规模集成电路系统，提出了一种功能通栅极和非易失性内存逻辑结构。残余极化电荷的跃迁和铁电电容器的电容耦合使得存储和开关功能合并到铁电电容器中。使用基于铁电的非易失性存储器可以切断泄漏电流。与采用0.6μm铁电/CMOS工艺的等效CMOS电路相比，将铁电电路应用于CAM实现中，动态功耗降低约一半，静态功耗降低1/22000。

项目成果

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameya: "DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage"IEEE Proceedings of the 30th International Symposium on Multiple-Valued Logic. 423-429 (2000)

Takahiro Hanyu、Hiromitsu Kimura、Michitaka Kameya：“具有电荷添加和电荷存储功能的基于 DRAM 单元的多值逻辑存储器 VLSI”第 30 届国际多值逻辑研讨会的 IEEE 论文集。

羽生貴弘, 亀山充隆: "2色2線式符号化に基づく非同期電流モード多値VLSIシステム"電子情報通信学会論誌C. Vol. J83-C, No.6. 463-470 (2000)

Takahiro Hanyu、Mitsutaka Kameyama：“基于双色双线编码的异步电流模式多级 VLSI 系统”《电子信息通信工程师学会杂志》C. Vol. J83-C，第 6. 463-470 期（ 2000)

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "Dynamic-Storage-Based Multiple-Valued Logic-in-Memory Circuit and Its Application"Proc. 2nd Korea-Japan Joint Symposium on Multiple-Valued Logic. 147-151 (2001)

Hiromitsu Kimura、Takahiro Hanyu、Michitaka Kameyama：“基于动态存储的多值逻辑内存电路及其应用”Proc。

Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: "Fully Source-Coupled Logic Based Multiple-Valued VLSI"Proc. of the 32nd IEEE Int. Symposium on Multiple-Valued Logic. 270-275 (2002)

Tsukasa Ike、Takahiro Hanyu、Michitaka Kameyama：“完全基于源耦合逻辑的多值 VLSI”Proc。

Hiromitsu Kimura, Takahiro Hanyu and Michitaka Kameyama: "Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System"IEICE Trans. Electron. E85-C, No.2. 288-296 (2002)

Hiromitsu Kimura、Takahiro Hanyu 和 Michitaka Kameyama：“基于动态存储的逻辑内存电路及其在细粒度流水线系统中的应用”IEICE Trans。