Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing

基于双轨多值数字计算的无互连超大规模集成电路系统

基本信息

批准号：
12480064
负责人：
KAMEYAMA MICHITAKA
金额：
$ 5.06万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2000
资助国家：
日本
起止时间：
2000 至 2002
项目状态：
已结题

项目摘要

The communication bottleneck between memories and logic modules is one of the most serious problems due to interconnection complexity in recent deep-submicron VLSI systems-on-a-chip. In the situation, high-performance and low-power VLSI circuit technologies suitable for multi-giga-hertz clock operations are expected to be developed. In this study, we proposed multiple-valued VLSI utilizing differential-pair circuit which has high-driving capability and ferroelectric-capacitor logic for low-power logic-in-memory VLSI.1.Development of the highest performance multiple-valued VLSIA novel-source-coupled logic style using multiple-valued signals is proposed for high-speed-low-power VLSI system. All the differential-pair circuits are driven by dual-rail signals, which we call "full source-coupled logic". Design and implementation results show that the performance of the full-source coupled logic circuit is very superior to the conventional multiple-valued source-coupled logic circuit. It is a useful circuit technology for multi-gigahertz and low-voltage operations.2.Ferroelectic Logic-in-Memory ArchitectureA functional pass gate and a nonvolatile logic-in-memory architecture are proposed for communication-bottleneck-free VLSI system. Transition of a remnant-polarization charge and capacitive coupling of a ferroelectric capacitor makes storage and switching functions which are merged into a ferroelectric capacitor. The use of ferroelectric-based non-volatile storage makes leakage currents cut off. Applying the ferroelectric based circuitry to CAM implementation results in about half dynamic power reduction and 1/22000 static power reduction in comparison with the equivalent CMOS implementation under 0.6μm ferroelecric/CMOS process.

记忆和逻辑模块之间的通信瓶颈是由于最近的深度增压VLSI系统中的互连复杂性，这是最严重的问题之一。在这种情况下，有望开发适合多基因 - 赫兹时钟操作的高性能和低功率VLSI电路技术。在这项研究中，我们提出了利用差速器电路的多价VLSI，该电路具有高驾驶能力和铁电能逻辑，用于低功率逻辑中的内存VLSI.1。使用多重质量的系统提出了高音，用于最高性能多效VLSIA多效VLSIA多效率VLSIA多效VLSIA多个新型逻辑样式。所有差分配电路都由双轨信号驱动，我们称之为“全源耦合逻辑”。设计和实现结果表明，全源耦合逻辑电路的性能非常优于常规的多值源耦合逻辑电路。它是用于多吉格尔兹和低压操作的有用电路技术。2。Feleleelectic in-Memory Architecturea功能通行门和非挥发性逻辑架构用于通信 - 无用的bottleneck-fleneck-fleneck-flsi System。铁电容器的残余电荷和电容耦合的过渡使存储和切换功能合并为铁电容器。基于铁电的非易失性存储的使用使泄漏电流切断。将基于铁电的电路应用于CAM实施，与在0.6μm铁核/CMOS过程下的同等CMOS实现相比，将大约一半动态功率降低和1/22000静态功率降低。