Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application
Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application
批准号:
13558026
负责人:
HANYU Takahiro
金额:
$8.7万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
2001
资助国家:
日本
项目状态:
已结题
起止时间:
2001 至 2004
中文摘要
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英文摘要
Dramatic advances in technology scaling give us the capability to realize a giga-scaled system-on-a-chip, while rapid increases in the wiring complexity and the global wiring delay has led to serious data-transfer bottleneck between separated logic modules and memories in current deep-submicron VLSI. Logic-in-memory structures, where storage functions are distributed over a logic-circuit plane, provide a key architecture for ensuring highly effective use of internal memory bandwidth. However, usual logic-in-memory VLSI becomes generally complicated, because of the hardware overhead involved in distributing storage elements. In this research, I have presented ferroelectric-based (FE-based) functional logic gates for highly parallel VLSI systems. In FE-based logic gates, since both non-volatile storage and switching functions are performed simultaneously in FE capacitors, chip size and a leakage current can be reduced. As a typical application of this circuit technology, a 54x54-bit pipe … More lined multiplier is implemented and its superior performance is demonstrated. Furthermore, I have also developed the improved ferroelectric-based logic circuit, called a "Complementary-Ferroelectric-Capacitor (CFC)" logic for low-power logic-in-memory VLSI. Using two FE capacitors where a pair of complementary data representations is stored, the voltage swing generated by capacitive coupling effect becomes large enough to perform the switching operation at the low supply voltage. Degradation of the non-volatile charge caused by the switching operation becomes small because the bias voltage appeared across the FE capacitor is always lower than its coercive voltage. As a typical example, a 32-bit content-addressable memory (CAM) is also implemented and its superior performance is demonstrated. Finally, a tunneling magnetoresistive (TMR)-based logic-in-memory circuit has been also proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability any logic functions between external inputs and stored inputs can be performed by using the TMR based resistor/transistor network The combination of a dynamic current-mode logic circuit and a TMR-based network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of a full adder is discussed, and its advantages are demonstrated. Less
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Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit
基于 DRAM 单元的多值内存逻辑电路的实现
DOI:
--
发表时间:
2002
期刊:
IEICE Trans.on Electronics E85-C
影响因子:
--
作者:
[H.Kimura]
通讯作者:
H.Kimura
Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI
近期深亚微米超大规模集成电路中多值技术的挑战
DOI:
--
发表时间:
2001
期刊:
IEEE 31st International Symposium on Multiple-Valued Logic 31
影响因子:
--
作者:
[山口類, 土屋映子, 樋口知之, T.Hanyu]
通讯作者:
T.Hanyu
Hiromitsu Kimura: "Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit"IEICE Transaction on Electronics. E85-C・10. 1814-1823 (2002)
Hiromitsu Kimura:“基于 DRAM 单元的多值逻辑内存电路的实现”IEICE E85-C·10 (2002)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
木村 啓明, 羽生 貴弘, 亀山 充隆: "ゲートレベルパイプライン用ロジックインメモリVLSIの構成"2001年電子情報通信学会ソサイエティ(エレクトロニクス). 69 (2001)
Hiroaki Kimura、Takahiro Hanyu、Mitsutaka Kameyama:“用于门级管道的内存中逻辑 VLSI 的配置”2001 IEICE 协会(电子)69 (2001)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
TMRロジックに基づくビット並列大小比較CAMの構成
基于TMR逻辑的位并行尺寸比较CAM的配置
DOI:
--
发表时间:
2005
期刊:
電子情報通信学会第2種研究会「多値論理とその応用」研究会技術研究報告 MVL-05・1
影响因子:
--
作者:
[Akira Mochizuki, 庄子耕平]
通讯作者:
庄子耕平
共 41 条
Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer Technique
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批准号:18300012
-
项目类别:Grant-in-Aid for Scientific Research (B)
-
资助金额:$11.01万
-
财政年份:2006
-
负责人:HANYU Takahiro
-
依托单位:
Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques
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批准号:15500029
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.43万
-
财政年份:2003
-
负责人:HANYU Takahiro
-
依托单位:
Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities
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批准号:12680324
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.37万
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财政年份:2000
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负责人:HANYU Takahiro
-
依托单位:
MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEM
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批准号:09044125
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项目类别:Grant-in-Aid for international Scientific Research
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资助金额:$1.98万
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财政年份:1997
-
负责人:HANYU Takahiro
-
依托单位:
Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application
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批准号:09558027
-
项目类别:Grant-in-Aid for Scientific Research (B).
-
资助金额:$7.49万
-
财政年份:1997
-
负责人:HANYU Takahiro
-
依托单位:
海外基金