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Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application

无传输瓶颈多值逻辑内存VLSI的实现及其应用

基本信息

批准号：
13558026
负责人：
HANYU Takahiro
金额：
$ 8.7万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2004
项目状态：
已结题

项目摘要

Dramatic advances in technology scaling give us the capability to realize a giga-scaled system-on-a-chip, while rapid increases in the wiring complexity and the global wiring delay has led to serious data-transfer bottleneck between separated logic modules and memories in current deep-submicron VLSI. Logic-in-memory structures, where storage functions are distributed over a logic-circuit plane, provide a key architecture for ensuring highly effective use of internal memory bandwidth. However, usual logic-in-memory VLSI becomes generally complicated, because of the hardware overhead involved in distributing storage elements. In this research, I have presented ferroelectric-based (FE-based) functional logic gates for highly parallel VLSI systems. In FE-based logic gates, since both non-volatile storage and switching functions are performed simultaneously in FE capacitors, chip size and a leakage current can be reduced. As a typical application of this circuit technology, a 54x54-bit pipe … More lined multiplier is implemented and its superior performance is demonstrated. Furthermore, I have also developed the improved ferroelectric-based logic circuit, called a "Complementary-Ferroelectric-Capacitor (CFC)" logic for low-power logic-in-memory VLSI. Using two FE capacitors where a pair of complementary data representations is stored, the voltage swing generated by capacitive coupling effect becomes large enough to perform the switching operation at the low supply voltage. Degradation of the non-volatile charge caused by the switching operation becomes small because the bias voltage appeared across the FE capacitor is always lower than its coercive voltage. As a typical example, a 32-bit content-addressable memory (CAM) is also implemented and its superior performance is demonstrated. Finally, a tunneling magnetoresistive (TMR)-based logic-in-memory circuit has been also proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability any logic functions between external inputs and stored inputs can be performed by using the TMR based resistor/transistor network The combination of a dynamic current-mode logic circuit and a TMR-based network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of a full adder is discussed, and its advantages are demonstrated. Less

技术规模的巨大进步使我们有能力实现千兆级片上系统，而布线复杂性和全局布线延迟的快速增加导致当前深亚微米VLSI中分离的逻辑模块和存储器之间存在严重的数据传输瓶颈。内存中逻辑结构（其中存储功能分布在逻辑电路平面上）提供了确保高效使用内部内存带宽的关键架构。然而，由于分配存储元素涉及硬件开销，通常的存储器中逻辑 VLSI 通常变得复杂。在这项研究中，我提出了用于高度并行 VLSI 系统的基于铁电（基于 FE）的功能逻辑门。在基于FE的逻辑门中，由于在FE电容器中同时执行非易失性存储和开关功能，因此可以减小芯片尺寸和漏电流。作为该电路技术的典型应用，实现了54x54位管道乘法器，并展示了其优越的性能。此外，我还开发了改进的基于铁电的逻辑电路，称为“互补铁电电容器（CFC）”逻辑，用于低功耗存储器逻辑VLSI。使用存储一对互补数据表示的两个 FE 电容器，电容耦合效应产生的电压摆幅变得足够大，足以在低电源电压下执行开关操作。由于FE电容器两端出现的偏置电压总是低于其矫顽电压，因此开关操作引起的非易失性电荷的劣化变小。作为典型示例，还实现了32位内容寻址存储器（CAM）并展示了其优越的性能。最后，还提出了一种用于低功耗 VLSI 系统的基于隧道磁阻 (TMR) 的逻辑内存电路。由于TMR器件被视为具有非易失性存储能力的可变电阻器，因此外部输入和存储输入之间的任何逻辑功能都可以通过使用基于TMR的电阻/晶体管网络来执行。动态电流模式逻辑电路和基于TMR的网络的组合使得无需稳定电流即可执行任何开关操作，从而实现节能。讨论了全加器的设计实例，并展示了其优点。较少的