Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application

无传输瓶颈多值逻辑内存VLSI的实现及其应用

基本信息

批准号：
13558026
负责人：
HANYU Takahiro
金额：
$ 8.7万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2004
项目状态：
已结题

项目摘要

Dramatic advances in technology scaling give us the capability to realize a giga-scaled system-on-a-chip, while rapid increases in the wiring complexity and the global wiring delay has led to serious data-transfer bottleneck between separated logic modules and memories in current deep-submicron VLSI. Logic-in-memory structures, where storage functions are distributed over a logic-circuit plane, provide a key architecture for ensuring highly effective use of internal memory bandwidth. However, usual logic-in-memory VLSI becomes generally complicated, because of the hardware overhead involved in distributing storage elements. In this research, I have presented ferroelectric-based (FE-based) functional logic gates for highly parallel VLSI systems. In FE-based logic gates, since both non-volatile storage and switching functions are performed simultaneously in FE capacitors, chip size and a leakage current can be reduced. As a typical application of this circuit technology, a 54x54-bit pipe … More lined multiplier is implemented and its superior performance is demonstrated. Furthermore, I have also developed the improved ferroelectric-based logic circuit, called a "Complementary-Ferroelectric-Capacitor (CFC)" logic for low-power logic-in-memory VLSI. Using two FE capacitors where a pair of complementary data representations is stored, the voltage swing generated by capacitive coupling effect becomes large enough to perform the switching operation at the low supply voltage. Degradation of the non-volatile charge caused by the switching operation becomes small because the bias voltage appeared across the FE capacitor is always lower than its coercive voltage. As a typical example, a 32-bit content-addressable memory (CAM) is also implemented and its superior performance is demonstrated. Finally, a tunneling magnetoresistive (TMR)-based logic-in-memory circuit has been also proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability any logic functions between external inputs and stored inputs can be performed by using the TMR based resistor/transistor network The combination of a dynamic current-mode logic circuit and a TMR-based network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of a full adder is discussed, and its advantages are demonstrated. Less

技术缩放的急剧进步使我们能够实现芯片上的GIGA标准系统，而接线复杂性的迅速增加和全球接线延迟导致了当前深水Micicron VLSI的独立逻辑模块和记忆之间的严重数据传输。逻辑中的内存结构，其中存储功能分布在逻辑电路平面上，为确保内部内存带宽的高效使用提供了关键体系结构。但是，由于涉及分发存储元素的硬件开销，因此通常的内存vlsi通常变得复杂。在这项研究中，我为高度并行VLSI系统提供了基于铁电（基于Fe的）功能逻辑。在基于FE的逻辑门中，由于非挥发性存储和开关功能都是在Fe电容器中执行的，因此可以降低芯片大小和泄漏电流。作为该电路技术的典型应用，实施了54x54位管……更衬里的乘数，并证明了其出色的性能。此外，我还开发了改进的基于铁电的逻辑电路，称为“互补-frolectric-capaCitor（CFC）”的逻辑，用于低功耗逻辑VLSI。使用两个Fe电容器，其中存储了一对互补数据表示，通过电容耦合效果产生的电压摆动变得足够大，可以在低电源电压下执行切换操作。由开关操作引起的非易失性电荷的降解变得很小，因为在Fe电容器上出现的偏置电压始终低于其强制电压。作为一个典型的例子，还实现了32位内容 - 可调地理的内存（CAM），并证明了其出色的性能。最后，还为低功率VLSI系统提出了基于隧道的磁性电阻（TMR）逻辑电路。由于TMR设备被认为是具有非挥发性存储能力的可变电阻器，可以通过使用基于TMR的电阻器/晶体管网络在外部输入和存储的输入之间执行任何逻辑功能，因此动态电流模式逻辑电路和TMR基于基于TMR的网络的组合使得在没有稳定的电流的情况下可以执行任何开关操作，从而可以执行任何开关操作。讨论了完整加法器的设计示例，并证明了其优势。较少的