Development of a Cluster Computing System for Evolutionary Synthesis of Hardware Algorithms

本研究计画旨在探讨利用一种新的演化最佳化技术--演化图产生（EGG），自动设计运算电路的可能性。以下是本项目的主要成果：1.为了有效地综合运算电路，基于并行处理的粗粒度模型，开发了一个并行EGG系统.构建了一个实验性的11节点Linux PC集群，用于实现并行EGG系统.提出了一种新的EGG系统，可用于合成各种不同的组件，如模拟/数字混合组件的异构网络。实验结果表明，引入终端颜色约束的EGG系统可以有效地减少电路布局的搜索空间.通过一系列实验来综合各种算术电路，包括常系数乘法器、常系数乘加法器、位串行加法器、位串行常系数乘法器、位串行常系数乘加法器和电流模式逻辑电路，评估所开发的EGG系统的性能。我们的观察表明，EGG是适合的电路设计问题，可以处理的电路图与多达50个节点。为了加速EGG的进化过程，提出了一种新的进化操作--“轮回”（transmigration），并进一步研究了一种可用于实际应用的通用EGG框架。

This research project is to investigate a possibility of designing arithmetic circuits automatically by employing a new evolutionary optimization, technique called Evolutionary Graph Generation(EGG). Listed below are major results of this project :1. A parallel EGG system based on the coarse-grained model of parallel processing was developed for synthesizing arithmetic circuits efficiently.2. An experimental 11-node Linux PC cluster was built for implementing the parallel EGG system.3. A new version of EGG system that can be used to synthesize heterogeneous networks of various different components such as analog/digital-mixed components was proposed. The new EGG system with terminal-color constraint was proved to be useful for reducing search space of possible circuit configurations.4. The performance of the developed EGG system was evaluated through a set of experiments for synthesizing various arithmetic circuits including constant-coefficient multipliers, constant-coefficient multiply-adders, bit-serial adders, bit-serial constant-coefficient multipliers, bit-seril constant-coefficient multiply-adders and current-mode logic circuits. Our observation shows that EGG is suitable for circuit design problems that can be handled by circuit graphs with up to 50 nodes.5. A new evolutionary operation called "transmigration" was investigated for accelerating EGG's evolution process.Further investigations on a general-purpose EGG framework for practical applications are being left as future research subjects.