Development of a Cluster Computing System for Evolutionary Synthesis of Hardware Algorithms

本研究旨在探讨利用一种新的进化优化技术--进化图生成(EGG)来自动设计算术电路的可能性。本课题的主要研究成果如下：1.为高效综合算术电路，开发了一个基于粗粒度并行处理模型的并行EGG系统。搭建了一个实验用的11节点Linux PC集群，实现了该并行EGG系统。提出了一种新版本的EGG系统，该系统可用于合成由模拟/数字混合组件等各种不同组件组成的异质网络。新的端子颜色约束的EGG系统被证明是有效的，可以减少可能电路配置的搜索空间。通过对常系数乘法器、常系数乘法器、位串联加法器、位串行恒系数乘法器、位串行恒系数乘法器和电流模式逻辑电路的综合实验，对所开发的EGG系统的性能进行了评估。我们的观察表明，EGG适合于可以由多达50个节点的电路图来处理的电路设计问题。为了加速鸡蛋的进化过程，研究了一种新的进化操作--“轮回”，但对具有实际应用价值的通用鸡蛋框架的进一步研究则是未来的研究课题。

This research project is to investigate a possibility of designing arithmetic circuits automatically by employing a new evolutionary optimization, technique called Evolutionary Graph Generation(EGG). Listed below are major results of this project :1. A parallel EGG system based on the coarse-grained model of parallel processing was developed for synthesizing arithmetic circuits efficiently.2. An experimental 11-node Linux PC cluster was built for implementing the parallel EGG system.3. A new version of EGG system that can be used to synthesize heterogeneous networks of various different components such as analog/digital-mixed components was proposed. The new EGG system with terminal-color constraint was proved to be useful for reducing search space of possible circuit configurations.4. The performance of the developed EGG system was evaluated through a set of experiments for synthesizing various arithmetic circuits including constant-coefficient multipliers, constant-coefficient multiply-adders, bit-serial adders, bit-serial constant-coefficient multipliers, bit-seril constant-coefficient multiply-adders and current-mode logic circuits. Our observation shows that EGG is suitable for circuit design problems that can be handled by circuit graphs with up to 50 nodes.5. A new evolutionary operation called "transmigration" was investigated for accelerating EGG's evolution process.Further investigations on a general-purpose EGG framework for practical applications are being left as future research subjects.