Development of a Cluster Computing System for Evolutionary Synthesis of Hardware Algorithms

这个研究项目是为了研究一种自动设计算术电路的可能性，通过采用一种新的进化优化技术，称为进化图生成（EGG）。以下是本项目的主要成果：基于并行处理的粗粒度模型，开发了一种并行EGG系统，以实现算法电路的高效综合。为实现并行EGG系统，构建了一个11节点的实验性Linux PC集群。提出了一种新型的EGG系统，该系统可用于模拟/数字混合等多种不同组件组成的异构网络的合成。结果表明，带有终端颜色约束的EGG系统能够有效地减少可能电路组态的搜索空间。通过对常系数乘法器、常系数乘法器、位-串加法器、位-串常系数乘法器、位-串常系数乘法器和电流型逻辑电路等多种算术电路的综合实验，对所开发的EGG系统的性能进行了评价。我们的观察表明，EGG适用于可由多达50个节点的电路图处理的电路设计问题。为了加速卵细胞的进化过程，研究了一种叫做“转代”的新进化操作。关于实际应用的通用EGG框架的进一步调查将作为未来的研究课题。

This research project is to investigate a possibility of designing arithmetic circuits automatically by employing a new evolutionary optimization, technique called Evolutionary Graph Generation(EGG). Listed below are major results of this project :1. A parallel EGG system based on the coarse-grained model of parallel processing was developed for synthesizing arithmetic circuits efficiently.2. An experimental 11-node Linux PC cluster was built for implementing the parallel EGG system.3. A new version of EGG system that can be used to synthesize heterogeneous networks of various different components such as analog/digital-mixed components was proposed. The new EGG system with terminal-color constraint was proved to be useful for reducing search space of possible circuit configurations.4. The performance of the developed EGG system was evaluated through a set of experiments for synthesizing various arithmetic circuits including constant-coefficient multipliers, constant-coefficient multiply-adders, bit-serial adders, bit-serial constant-coefficient multipliers, bit-seril constant-coefficient multiply-adders and current-mode logic circuits. Our observation shows that EGG is suitable for circuit design problems that can be handled by circuit graphs with up to 50 nodes.5. A new evolutionary operation called "transmigration" was investigated for accelerating EGG's evolution process.Further investigations on a general-purpose EGG framework for practical applications are being left as future research subjects.