Set-Valued-Logic VLSI Architecture for Highly Parallel Computation

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Interconnection problems have been recognized as basic limitations in present-day VLSI systems. This research project is to investigate a possibility of solving the interconnection problems by employing new VLSI architectures based on multiple-valued logic (MVL) and set-valued logic (SVL). Listed below are major results of this project :1. The basic SVL gates employing binary m-sequences as information carriers were proposed.A systematic technique for synthesizing S VL circuits with the basic logic gates was investigated.2. A highly reliable SVL system employing distributed signal representation with binary m-sequences was proposed.3. A method of implementing SVL circuits using bi-directional current-mode CMOS technology was proposed. A 9x9-pixel template matching circuit for image processing was fabricated with 0.6um CMOS technology. It was shown that 30% reduction in chip area and 78% reduction in wire area could be achieved by SVL technology for 40x40-pixel template matching.4. A new type of highly parallel neural network architecture employing m-sequences as signal carriers was proposed.5. The concept of SVL was extended into a general framework of intra/inter-chip CDMA communication using orthogonal information carriers. A phase-offset-error-free CDMA technique based on multiple-valued m-sequences was investigated for efficient data transmission in VLSI systems.6. Various hardware algorithms and VLSI architectures based on MVL were also investigated to compare fundamental properties of MVL and SVL.Our initial observation shows that SVL (or CDMA) is suitable for analog signal transmission/processing as well as large-scale inter-chip communication, while MVL is suitable for digital arithmetic computation with lower processing granularity.Further investigations on MVL/SVL-based VLSI architectures for large-scale applications are being left as future research subjects.