Development of a Real-Time Reconfigurable Signal Processor for Image Recognition

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Recently, we have proposed a DSP-oriented image recognition algorithm based on Phase-Only Correlation (POC). For applying the proposed algorithm to practical image recognition tasks, high-speed computation of real/complex-mixed data is essential. In this research project, we investigated a signal processor architecture for POC-based image recognition. Non-binary data representations, such as redundant complex number systems and high-radix redundant number systems, are employed to perform fast real/complex-mixed computation. We have developed the key components for the signal processor as listed below:1. A real/complex reconfigurable arithmetic unit, that can change its structure for three different operation modes, has been proposed and fabricated in 0.5um CMOS. The three modes realize complex-number multiplication, double-length real-number multiplication, and real-number multiply-add operation. The reconfiguration overhead is significantly low, which corresponds to only 8.9% increase … More of transistor count.2. A redundant complex multiplier has been proposed and fabricated in 0.5um CMOS. The chip area, interconnect delay and power consumption are reduced to 33.7%, 16.9% and 18.4%, respectively, compared with a complex-number multiplier designed by a standard logic synthesis tool.3. A configurable multiply-adder based on SW (Signed-Weight) arithmetic has been proposed and fabricated in 0.35um CMOS. The fabricated chip can perform FIR filtering with high sampling-rate around 10MHz-100MHz.4. A parallel divider and a CORDIC vector rotator for 3D image processing have been proposed and fabricated. The use of high-radix redundant number systems makes possible low-latency implementations of iterative arithmetic operations.In addition to the above results, various applications of POC-based image recognition have been investigated. We developed a 3D (stereo) vision system using hierarchical phase-only matching, and clarified architectural requirements toward the implementation of a new signal processor for 3D measurement and object recognition. Less