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A LOW ENERGY DESIGN METHOD USING MULTI-CONTEXT RECONFIGURATION

A LOW ENERGY DESIGN METHOD USING MULTI-CONTEXT RECONFIGURATION
一种利用多上下文重构的低能耗设计方法
批准号:
16560303
负责人:
IIDA Masahiro
金额:
$2.3万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2004
资助国家:
日本
项目状态:
已结题
起止时间:
2004 至 2005

项目摘要

项目成果

IIDA Masahiro的其他基金

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中文摘要
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英文摘要
Reconfigurable computing is computer processing with highly flexible computing fabrics. In the last decade there was a renaissance in this area of research with many proposed reconfigurable architectures developed. Most of these have a two-dimensional logic block array architecture, and they have a memory that stores two or more contexts. These devices support run-time reconfiguration by rapidly switching between contexts. However, in compared with ASIC, dynamic reconfigurable devices are generally not considered to be power efficient because they use a large number of transistors to provide programmability. Large power consumption therefore becomes a constraining factor in device design. Power optimization has attracted increase attention due to the rapid growth of personal wireless communications, battery powered devices and portable digital applications.It is our aim to reduce the power consumption using dynamic reconfiguration. The dynamic reconfigurable devices enable us to reconf … More igure circuits according to the current usage conditions. We designed smaller circuits that may be omitted if their function is not used at some point in time in the original circuit. We expected that energy savings could be realized by reconfiguration of these smaller circuits, since the energy consumption of the smaller circuits is usually low.In this project, we estimate the energy consumption in the operation and reconfiguration of the circuits. Then, the energy consumption of the smaller circuits is compared with that of the original circuit. We show that execution with reconfiguration the smaller circuits reduces the energy consumption. The energy consumption was reduced by an average of about 71% in the case of matching circuit, and a maximum of about 35% for FIR filters. Moreover, the operating frequency of the smaller circuits is higher than original circuit.However, it is difficult to design smaller circuits that are suitable for various applications. We propose a unique technique to making smaller circuits based on logic gate reduction. The basic idea of this technique is that logic gates are reducible if the input is set to a constant. The resulting circuits are called data-dependent circuits. We design the data-dependent circuits and reconfigure them in accordance with the conditions of usage ; self-reconfiguration is also possible. We apply our method to a DCT module of JPEG encoder. As a result of evaluation, the energy consumption was reduced by a maximum of about 16.5%. Less
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DOI: --
发表时间: 2004
期刊: 電子情報通信学会コンピュータシステム研究専門委員会所属第2種研究会 第4回リコンフィギャラブルシステム研究会論文集
影响因子: --
作者: [今井茂毅, 飯田全広, 末吉敏則]
通讯作者: 末吉敏則
DOI: --
发表时间: 2004
期刊: 第17回 回路とシステム軽井沢ワークショップ論文集
影响因子: --
作者: [池田祐介, 木幡雅貴, 飯田全広, 末吉敏則]
通讯作者: 末吉敏則
DOI: 10.1109/fpl.2005.1515700
发表时间: 2005-10
期刊: International Conference on Field Programmable Logic and Applications, 2005.
影响因子: --
作者: [Hisashi Tsukiashi;M. Iida;T. Sueyoshi]
通讯作者: Hisashi Tsukiashi;M. Iida;T. Sueyoshi
A Low Power Design Method using Multi-context Dynamic Reconfiguration
一种使用多上下文动态重配置的低功耗设计方法
DOI: --
发表时间: 2005
期刊: Commemorative International Technical Conference on Cicuits/Systems, Coiputers and Communications(ITC-CSCC2005) 2
影响因子: --
作者: [IMAI, S]
通讯作者: S
14
    A study on low delay network topology for a large scale parallel computing system
    • 批准号:
      17K00082
    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
      $2.91万
    • 财政年份:
      2017
    • 负责人:
      IIDA Masahiro
    • 依托单位:
    Research on programming model for Reconfigurable Systems
    • 批准号:
      23650018
    • 项目类别:
      Grant-in-Aid for Challenging Exploratory Research
    • 资助金额:
      $1.58万
    • 财政年份:
      2011
    • 负责人:
      IIDA Masahiro
    • 依托单位:
    A Study of High Dependability Reconfigurable Logic Architecture
    • 批准号:
      23300017
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $10.23万
    • 财政年份:
      2011
    • 负责人:
      IIDA Masahiro
    • 依托单位:
    A study of the integrated EDA tools for reconfigurable logic
    • 批准号:
      18300015
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $9.85万
    • 财政年份:
      2006
    • 负责人:
      IIDA Masahiro
    • 依托单位: