Photonic Reservoir Computing enabled by Active Silicon Micro-Rings

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Neuromorphic signal processing (NSP) has been emerging in recent years as an alternative to classical signal processing algorithms and processes. Among others, optical communication systems can benefit from NSP due to its ability to compensate nonlinear impairments. Instead of programming the processing tasks explicitly into a digital signal processor (DSP) or field-programmable gate array (FPGA) NSP takes a fundamentally different approach to signal processing. It uses artificial neural networks (ANN), where the machine is trained to learn the basic physical model behind the processing task and to act accordingly. However, it is very challenging to implement such ML techniques for real-time signal processing at the required line rates of up to several hundred Gb/s. This will become even more difficult in the future when signal line rates (and associated bandwidths) further scale exponentially. It can be currently foreseen that the signal bandwidth of electronic circuits will be limited in the range of 100 GHz to a maximum of a few hundred GHz in the medium term. Thus, it is desirable to shift some signal processing tasks to the optical domain, where a much higher bandwidth of multiple THz is available already today.Photonic reservoir computing (RC) has the ability to be implemented as scalable hardware, which is unique among other ANNs. In RCs, only the input and output of the (artificial neural) network need to be adaptive and not the network itself. In fact, the interconnections are considered to be a ‘black box’. Since the nonlinear transformation to a higher dimensional state is done inside the reservoir, the output becomes a linear problem. The primary objective of the proposed research project is to analyze, fabricate and demonstrate a photonic reservoir computer based on a silicon micro-ring structure to compensate for the impairments of a fiber-optic transmission system. To achieve the specified objective, a silicon photonics chip using CMOS compatible technology for the realization of the reservoir computer will be designed and manufactured in a commercially available foundry. Intensive numerical simulations are required to optimize the design of the ring resonator structure. The fabricated chip will be characterized and integrated into an experimental system testbed.