Power-fail aware byte-addressable virtual non-volatile memory (PAVE)

电源故障感知字节可寻址虚拟非易失性存储器 (PAVE)

• 批准号: 501993201
• 负责人: Professor Dr.-Ing. Jörg Nolte
• 金额: --
• 依托单位: Lehrstuhl für Informatik 4: Verteilte Systeme und Betriebssysteme
• 依托单位国家: 德国
• 项目类别: Priority Programmes
• 资助国家: 德国
• 项目状态: 未结题
• 来源: https://gepris.dfg.de/gepris/projekt/501993201?language=en
• 关键词: Power; fail; aware; byte; addressable

Virtual memory (VM) subsystems blur the distinction between storage and memory such that both volatile and non-volatile data can be accessed transparently via CPU instructions.Each and every VM subsystem tries hard to keep highly contended data in fast volatile main memory to mitigate the high access latency of secondary storage, irrespective of whether the data is considered to be volatile or not.The recent advent of byte-addressable NVRAM does not change this scheme in principle, because the current technology can neither replace DRAM as fast main memory due to its significantly higher access latencies, nor secondary storage due to its significantly higher price and lower capacity.Thus, ideally, VM subsystems should be NVRAM-aware and be extended in such a way that all available byte-addressable memory technologies can be employed to their respective advantages.By means of an abstraction anchored in the VM management in the operating system, legacy software should then be able to benefit unchanged and efficiently from byte-addressable non-volatile main memory.Due to the fact that most VM subsystems are complex, highly-tuned software systems, which have evolved over decades of development, we follow a minimally invasive approach to integrate NVRAM-awareness into an existing VM subsystem instead of developing an entirely new system from scratch.NVRAM will serve as an immediate DRAM substitute in case of main memory shortage and inherently support processes with large working sets.However, due to the high access latencies of NVRAM, non-volatile data also needs to be kept at least temporarily in fast volatile main memory and the volatile CPU caches, anyway.Our new VM subsystem - we want to adapt FreeBSD accordingly - then takes care of migration of pages between DRAM and NVRAM, if the available resources allow.Thus, the DRAM is effectively managed as a large software-controlled volatile page cache for NVRAM.Consequently, this raises the question of data losses caused by power outages.The VM subsystem therefore needs to keep its own metadata in a consistent and recoverable state and modified pages in volatile memory need to be copied to NVRAM to avoid losses.The former requires an extremely efficient transactional mechanism for modifying of complex, highly contended VM metadata,while the latter must cope with potentially large amounts of modified pages with limited energy reserves.

虚拟存储器（VM）子系统模糊了存储和存储器之间的区别，使得易失性和非易失性数据都可以通过CPU指令透明地访问。每个VM子系统都努力将高度竞争的数据保持在快速易失性主存储器中，以减轻辅助存储的高访问延迟，而不管数据是否被认为是易失性的。字节可寻址NVRAM的最近出现在原则上没有改变这种方案，因为当前技术既不能由于DRAM的显著更高的访问延迟而取代DRAM作为快速主存储器，也不能由于DRAM的显著更高的价格和更低的容量而取代辅助存储器。因此，理想地，VM子系统应该是NVRAM感知的，并且以这样一种方式进行扩展，即所有可用的字节-可寻址存储器技术可以用于它们各自的优点。通过在操作系统中的VM管理中锚定的抽象，由于大多数VM子系统是复杂的、高度调优的软件系统，其已经在几十年的发展中进化，我们采用微创方法集成NVRAM，在主存储器不足的情况下，NVRAM将作为DRAM的直接替代品，并且固有地支持具有大工作集的进程。然而，由于NVRAM的高访问延迟，非易失性数据也需要至少暂时保存在快速易失性主存储器和易失性CPU缓存中。我们的新VM子系统-我们希望相应地调整FreeBSD-然后在可用资源允许的情况下负责DRAM和NVRAM之间的页面迁移。因此，DRAM作为NVRAM的大型软件控制的易失性页面高速缓存被有效地管理。因此，因此，VM子系统需要将自己的元数据保持在一致和可恢复的状态，并将修改后的页面保持在易失性存储器需要复制到NVRAM以避免丢失。前者需要极其高效的事务机制来修改复杂的、高度争用的VM元数据，而后者必须以有限的能量储备来科普潜在的大量修改页面。