Compiler-Directed Code Tiling for Higher Program Performance and Predictability on Multi-Level Memory Hierarchies

编译器控制的代码平铺可提高多级内存层次结构的程序性能和可预测性

• 批准号: DP0452623
• 负责人: Prof Jingling Xue
• 金额: $ 10.45万
• 依托单位: The University of New South Wales
• 依托单位国家: 澳大利亚
• 项目类别: Discovery Projects
• 财政年份: 2004
• 资助国家: 澳大利亚
• 起止时间: 2004-07-01 至 2007-12-31
• 项目状态: 已结题
• 来源: https://dataportal.arc.gov.au/RGS/Web/Grants/DP0452623
• 关键词: Compiler; Directed; Code; Tiling; Higher

Programming languages invariably induce a perception of memory as being flat, whereas actual computers are being equipped increasingly with deep memory hierarchies to overcome the ever-widening performance gap between processors and memories. This mismatch can result in low locality of reference and poor performance. This project will develop a new array layout transformation, called data tiling, used in tandem with loop tiling to achieve significantly improved performance gains (and predictability) for array-dominated applications on multi-level memory hierarchies. We will explore this joint restructuring to obtain higher performance and predictability for whole programs, kernel libraries, iterative stencil codes and embedded applications.

编程语言总是让人觉得内存是扁平的，而实际的计算机正越来越多地配备深度内存层次结构，以克服处理器和内存之间不断扩大的性能差距。这种不匹配可能导致低局部引用和较差的性能。该项目将开发一种新的数组布局转换，称为数据平铺，与循环平铺一起使用，以显着提高在多级内存层次结构上以数组为主的应用程序的性能（和可预测性）。我们将探索这种联合重组，以获得整个程序、内核库、迭代模板代码和嵌入式应用程序的更高性能和可预测性。