Compiler-Directed Code Tiling for Higher Program Performance and Predictability on Multi-Level Memory Hierarchies

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Programming languages invariably induce a perception of memory as being flat, whereas actual computers are being equipped increasingly with deep memory hierarchies to overcome the ever-widening performance gap between processors and memories. This mismatch can result in low locality of reference and poor performance. This project will develop a new array layout transformation, called data tiling, used in tandem with loop tiling to achieve significantly improved performance gains (and predictability) for array-dominated applications on multi-level memory hierarchies. We will explore this joint restructuring to obtain higher performance and predictability for whole programs, kernel libraries, iterative stencil codes and embedded applications.