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A Study on Parallel Processing for VLSI Layout

VLSI布局并行处理的研究

基本信息

批准号：
02650270
负责人：
YOSHIDA Noriyoshi
金额：
$ 1.41万
依托单位：
Hiroshima University
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (C)
财政年份：
1990
资助国家：
日本
起止时间：
1990 至 1991
项目状态：
已结题

项目摘要

Results obtained in this research are summarized below.1. Development of algorithms for building-block layout : We developed a hierarchical floorplanning method which determines floorplan and detailed routing together in a hierarchial fashion. Furthermore, we devised an optimal linear time algorithm for channel pin assignment.2. Development of algorithms for gate-array layout : We developed an algorithm for timing-driven placement of cells in a gate-array chip. Furthermore, we devised a global routing method for large gate-array with over-the-cell routing. These methods can be easily modified to parallel algorithms, which can obtain better results in short computation time compared with existing methods.3. Development of a parallel algorithm development system : We implemented a simulator for evaluating parallel algorithms on a workstation. Computation model of the simulator was a shared memory shared bus type multiprocessor. The simulator can produce a detailed simulation data such as hit ratio of cache. We also developed a processor scheduling algorithm for DOACROSS parallelization of sequential loops so that efficient execution of parallel algorithms becomes possible.4. Development of parallel layout algorithms : We devised a parallel algorithm for the problem of partitioning a graph, which is one of the fundamental problems in VLSI layout design. The algorithm was evaluated from both theoretical and experimental points of view. We also developed a parallel module placement algorithm based on a parallel graph partitioning algorithm. These algorithms showed that introducing parallel processing into VLSI layout design is quite effective to obtain good design in a short design time.

本研究取得的成果总结如下.积木式布局算法的开发：我们开发了一种分层布图规划方法，该方法以分层的方式确定布图规划和详细布线。此外，我们设计了一个最佳线性时间的通道管脚分配算法.门阵列布局算法的开发：我们开发了一种用于在门阵列芯片中时序驱动单元布局的算法。此外，我们设计了一个全局布线方法，为大型门阵列与过的单元布线。这些方法可以很容易地修改为并行算法，与现有方法相比，可以在较短的计算时间内获得更好的结果.并行算法开发系统的发展：我们实现了一个模拟器上的工作站上评估并行算法。该模拟器的计算模型为共享内存共享总线型多处理机。该模拟器可以产生一个详细的模拟数据，如命中率的缓存。我们还开发了一个处理器调度算法的DOACROSS并行顺序循环，使并行算法的有效执行成为可能.并行布局算法的发展：我们设计了一个并行算法的问题，划分一个图，这是在VLSI布局设计的基本问题之一。该算法从理论和实验的角度进行了评估。我们还开发了一个并行模块布局算法的基础上的并行图划分算法。这些算法表明，在VLSI版图设计中引入并行处理是在较短的设计时间内获得好的设计结果的有效方法。