Intelligent Image Processor based on neuron-MOS image sensor merged architecture
Intelligent Image Processor based on neuron-MOS image sensor merged architecture
批准号:
06402038
负责人:
SIBATA Tadshi
金额:
$15.3万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (A)
财政年份:
1994
资助国家:
日本
项目状态:
已结题
起止时间:
1994 至 1995
中文摘要
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英文摘要
An image captured on an image sensor chip has an enormous amount of information. It is spatially two-dimensional and, if motion is concerned, it becomes three dimensional because time axis is added. It is almost impossible to perform a real-time recognition of the image by a sequential computation on general purpose computers even if it is the most advanced one of today. The purpose of this research is to develop a basic hardware of integrated-circuit systems that can perform real-time intelligent image recognition. Two integrated circuits have been developed that can real-time detect and trace the movement of an object using a high-functionality device called Neuron MOS transistor (vMOS) as a key circuit element. The processing is conducted on two sets of one-dimensional data obtained by projecting a two-dimensional image data onto x- and y-axs. As a result, it has become possible to detect the motion vector between two successive frames within a few hundred nono secondS,which usually takes about a few tens miliseconds using plural of dedicated DSP chips. We also developed a circuit which can real-time track the position of the center of mass of a moving image. Owing to the vMOS circuit technology, such a processing can be done in several tens nano seconds using a very simple hardware. The characteristic feature of the vMOS integrated circuits is that it accepts analog signals, processing in analog/digital merged hardware computation and yields answers all in digital format. Therefore vMOS circuit technology provides an ideal interfacing between the real world and computer world.
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T.Ohmi: "Intelligeme Implementation on Silicon Based on Four-Terminal Device Electronics" Proc.20th International Conf.on Microelectronics(MILE'95) Nis,Serbia,Sert.,1995. 11-18 (1995)
T.Ohmi:“基于四端子器件电子学的硅智能实现”Proc.20th International Conf.on Micro electronics(MILE95) Nis,塞尔维亚,Sert.,1995。
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K.Kotani: "Clocked-neuron MOS logic Circuits employing autothreshold adjustment" Digest of Technical Papers,IEEE International Solid-State Circuit Conference. 320-321 (1995)
K.Kotani:“采用自动阈值调整的时钟神经元 MOS 逻辑电路”技术论文文摘,IEEE 国际固态电路会议。
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T.Ohmi and T.Shibata: ""Intellligence Implementation on Silicon Based on Four-Terminal Device Electronics"" Proceedings, 20th International Conference on Microelectronics (MIEL'95), Nis, Servia, September. Vol.1. 11-18 (1995)
T.Ohmi 和 T.Shibata:“基于四端子器件电子学的硅智能实现”论文集,第 20 届国际微电子会议 (MIEL95),塞尔维亚尼什,9 月。
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T.Ohmi and T.Shibata: ""Intelligence Implementation on Silicon Based on Four-Terminal Device Electronics"" accepted for publication in the Special issue of the Microelectronics Journal "Advances in Microelectronics". (to be published).
T.Ohmi 和 T.Shibata:“基于四端子器件电子学的硅智能实现”接受发表在微电子杂志“Advances in Micro electronics”的特刊上。
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K.Kotani: "DC-Current free low-power A/D Conuerfer Cirautry Using Dynamic Latch Comparators with divided capacitance voltage rolerence" 1996 IEEE International Symposium on Circuit and Systems (ISCAS96). 205-208 (1996)
K.Kotani:“使用带有分压电容电压角色的动态锁存比较器的无直流电流低功耗 A/D Conuerfer Cirautry”1996 年 IEEE 国际电路与系统研讨会 (ISCAS96)。
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