Research on a Very Large Data Path processor

超大型数据路径处理器的研究

• 批准号: 07458052
• 负责人: TANAKA Hidehiko
• 金额: $ 4.35万
• 依托单位: University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1995
• 资助国家: 日本
• 起止时间: 1995 至 1997
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-07458052/
• 关键词: dataflow anaysis; VLDP; branch handling; speculative execution; dynamic prefetch; address prediction; data traffic; ILP; VLDP; 大規模データパスプロセッサ; 分岐予測; 並列度; タイム管理モジュール; 処理ステップオ-ガナイザ; マッピングモジュール; データフロー変換; メモリアロケイタ

In this research, we took a close look at parallelism extraction, handling of control dependencies, and enhanced memory system, which could be the key technologies of Very Large Data Path (VLDP) architecture. The outcome we gained are as follows.Firstly, we examined the characteristics of parallelism restricted by control dependencies and data dependencies : we found that the VLDP architecture can achieve dozens of times as much performance as conventional scalar processors can, when we have both the perfect branch predictor and the complete memory system.Secondly, we examined suitable branch handling for the VLDP architecture. This branch handling needs to treat simultaneously plural control flow and needs to fetch instructions speculatively across many branches. For this purpose, we proposed a new branch predictor named multi-level branch predictor and examined its behavior.Thirdly, we improved a memory system based on the cache mechanism by utilizing a newly proposed data prefetch algorithm that predicts a referenced address based on the evaluation of a linear function. We confirmed this new system lessens overhead of memory references. Moreover we examined the traffic between the memory and the datapath, which tends to be a bottleneck for high performance processors. We showed that this traffic is reduced to less than half of conventional scheme when the VLDP architecture utilizes the direct data transfer among the remarkable number of ALUs.From these results, technological issues of VLDP architecture are made clear and we confirmed the possibility of performance improvement.

在这项研究中，我们仔细研究了并行提取，控制依赖的处理，和增强的存储系统，这可能是非常大的数据路径（VLDP）架构的关键技术。主要研究结果如下：首先，我们分析了控制依赖和数据依赖约束下的并行特性：当我们同时具有完美的分支预测器和完整的存储系统时，VLDP结构可以获得几十倍于传统标量处理器的性能;其次，我们分析了适合VLDP结构的分支处理。这种分支处理需要同时处理多个控制流，并且需要跨许多分支推测性地获取指令。为此，我们提出了一种新的分支预测器--多级分支预测器，并分析了它的行为。第三，我们改进了一个基于该高速缓存机制的存储系统，提出了一种新的数据预取算法，该算法基于线性函数的求值来预测引用地址。我们确认这个新系统减少了内存引用的开销。此外，我们研究了内存和数据路径之间的流量，这往往是高性能处理器的瓶颈。我们发现，当VLDP架构利用大量ALU之间的直接数据传输时，这种流量减少到传统方案的一半以下。从这些结果来看，VLDP架构的技术问题是明确的，我们证实了性能改善的可能性。