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Research on Reconfigurable General Purpose Co-processor Systems and Their Optimized Hardware/Software Codesign Compiler

可重构通用协处理器系统及其优化的软硬件协同设计编译器研究

基本信息

批准号：
07458060
负责人：
WATANABE Katsumasa
金额：
$ 3.71万
依托单位：
Nara Institute of Science and Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1995
资助国家：
日本
起止时间：
1995 至 1997
项目状态：
已结题

项目摘要

We have investigated computer systems with reconfigurable general purpose co-processors, and the hardware/software codesign environment for the systems. The results of our research are as follows :1. We have proposed a reconfigurable coprocessor architecture made of FPGAs (Field Programmable Gate Arrays), a cache memory, and a bus interface.2. We have designed and implemented a prototype of the co-processor for Sun workstations. The coprocessor includes 4 FPGAs, a 1 MB cache memory, and a bus interface with a hardware queue.3. We proposed a hardware/software codesign environment for the computer system with the co-processor. We have investigated the system description languages and the co-operation method between the main processor and the co-processor.4. We have designed and implemented the codesign environment from C programs for the coprocessor system. The hardware/software codesign compiler accepts a C program and estimates the execution time and the hardware costs of each function … More when the function is implemented as a hardware. The compiler also estimates the execution time of the function with the software implementation. Then the compiler decides the implementation method of each function.5. We have investigated the optimization method of C programs to be implemented as hardware modules on FPGAs. We have introduced hardware independent optimization methods such as the loop-unrolling, the variable bit-length reduction, the function expansion, ets., optimization methods such as the 4-1 LUT (Look-Up Table) based hardware estimation method, the marge method of bit-level operations, etc.6. We have tested several algorithms on the prototype of the codesign system, which include lexical analysis, sorting, and several graphic applications. We have found that the FPGA based co-processor is useful for the fast execution of programs, when the program include the parallel-if structure or the bit-level operations.In the future, we would like to investigate context switching on the co-preoessor system, and dynamic reconfigurability of the co-processor. Less

我们已经调查了计算机系统与可重构的通用协处理器，和系统的硬件/软件协同设计环境。研究结果如下：1.提出了一种由FPGA（现场可编程门阵列）、高速缓冲存储器和总线接口构成的可重构协处理器结构.我们已经设计并实现了一个原型的协处理器的Sun工作站。该协处理器包括4个FPGA、1 MB高速缓存和一个带硬件接口的总线接口.我们提出了一个硬件/软件协同设计环境的计算机系统与协处理器。研究了系统描述语言和主、协处理器之间的协同工作方法。我们设计并实现了协处理器系统的C语言协同设计环境。硬件/软件协同设计编译器接受C程序并估计每个函数的执行时间和硬件成本 ...更多信息当该功能被实现为硬件时。编译器还估计软件实现的函数的执行时间。然后由编译器决定每个函数的实现方法.我们已经研究了C程序的优化方法，以实现在FPGA的硬件模块。介绍了与硬件无关的优化方法，如循环展开、可变位长度缩减、函数扩展等，优化方法，例如基于4-1 LUT（查找表）的硬件估计方法、位级操作的Marge方法等。我们已经测试了几个算法的原型的协同设计系统，其中包括词法分析，排序，和几个图形应用程序。我们发现，当程序包含并行if结构或位级操作时，基于FPGA的协处理器对于程序的快速执行是有用的，在未来，我们希望研究协处理器系统上的上下文切换，以及协处理器的动态可重构性。少