Hardware/Software Codesign Flow of the 2020s

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Hardware/Software Codesign Flow of the 2020s According to ITRS, we can foresee SoCs with 1000 or more processors on a single chip in the year 2020. These SoCs will populate the embedded systems of tomorrow (GPS, smartphones, video players, airplane electronics, etc.). Designing and verifying a hardware solution with such a huge number of processing elements, with even more complex software including hundreds of applications to exploit it, will be an enormous challenge. Programmability, adaptivity, scalability, physical constraints, reliability and fault tolerance are among the issues that must be addressed to minimize the cycle time and the development cost of these complex future systems. Hardware/Software (HW/SW) co-design investigates the concurrent design of hardware and software components, by proposing a design and verification flow for simultaneously creating hardware and software that comprises an embedded system. In recent years, and more so in the future, HW/SW co-design will be a must for engineers (hardware, software and system) involved in the development of complex automotive networked systems, aerospace and avionics systems, manufacturing systems, and embedded systems in general. The main objective of this proposal is to explore and experiment with the HW/SW co-design flow of the 2020s by focusing on five main issues: 1) Exploring heterogeneity of these multi-processor architectures and their abstraction; 2) Automated of the architectural exploration; 3) Importing legacy RTL and third-party IP blocks within a HW/SW co-design flow; 4) Improvement of the HW/SW co-verification methodology and 5) A complete HW/SW co-design and co-verification flow for the aerospace and multimedia industries.