权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

New Design and Implementation of On Senson Compression

On Senson 压缩的新设计和实现

基本信息

批准号：
07555117
负责人：
AIZAWA Kiyoharu
金额：
$ 4.8万
依托单位：
The University of Tokyo
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
1995
资助国家：
日本
起止时间：
1995 至 1996
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-07555117/
关键词：
Image Sensor Intelligent Sensor Image compression Smart Sensor Computational Sensor CMOS Sensor

项目摘要

In this research, we propose a novel image sensor on which image signal can be compressed Since image single is compressed on the imager plane by making use of parallel nature of image signals, the amount of sigual read out from the imager can be significantly reduced. Thus, the proposed sensor can be potentially applied to high pixel rate cameras and processing systems which require very high speed imaging and very high resolution for real time imaging ; the very high bandwidth is the fundamental limitation for feasibility of those high pixel rate sensors and processing systems.Conditional replenishment algorithm is employed for the compression scheme ; it detects temporally changing pixels as active pixels and output those active pixels. Two architechtures of compression sensors listed below were investigated. The prototypes based on both approaches operate more than 1000 frames per second.(1) Pixel Parallel ArchitectureAll the required computational elements, that are detection, rate control and address encoding, were implemented. A prototype VLSI which has 32 x 32 pixels was examined.(2) Column Parallel ArchitectureIn order to improve fill factor and power dissipation, a column parallel architecture were investigated. A prototype VLSI which has 32 x 32 pixels was implemented and shows good quality of pitures.

在本研究中，我们提出了一种新型的图像传感器，其上的图像信号可以被压缩。由于利用图像信号的并行性质，图像信号被压缩在成像器平面上，所以从成像器读出的信号量可以被显著地减少。因此，该传感器可应用于需要非常高速成像和非常高分辨率的真实的时间成像的高像素速率相机和处理系统中，非常高的带宽是这些高像素速率传感器和处理系统可行性的根本限制。它检测时间上变化的像素作为有效像素并输出这些有效像素。研究了下面列出的两种压缩传感器结构。基于这两种方法的原型每秒运行超过1000帧。(1)像素并行结构实现了检测、码率控制和地址编码等所有需要的计算单元。一个原型的超大规模集成电路，具有32 × 32像素进行了检查。(2)列并行结构为了提高填充因子和功耗，研究了一种列并行结构。实现了一个32 × 32像素的VLSI原型，并显示出良好的图形质量。