DEVELOPMENT OF VACUUM MICRO DEVICES OPARATING AT LOW VOLTAGES WITH HIGH CURRENT DENSITY

低电压高电流密度真空微型器件的研制

• 批准号: 07650400
• 负责人: MURATA Kenji
• 金额: $ 1.41万
• 依托单位: OSAKA PREFECTURE UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 1995
• 资助国家: 日本
• 起止时间: 1995 至 1996
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-07650400/
• 关键词: FIELD EMITTER ARRAY; FIELD EMISSION; NICKL; SILICON; HOLOGRAFIC LITHOGRAPHY; LIFT OFF; 電子ビーム蒸着; モリブデン; タングステン; 微細加工

It is important to develop a field emitter array (FEA) which works at low voltages with high current density. Both the gap between the emitter and the gate and the radius of the emitter curvature have to be made small in order to decrease the operating voltage. The emitter density has to be increased in order to obtain a high current density. The following experiments are performed in order to develop such novel FEAs.(i) Fabrication of lateral nickel FEAs.Since fine resist patterns have to be fabricated with high resolution, we use optical projection lithography with an oil immersion lens which has a high numerical aperture of 1.25. Nickel FEAs are fabricated by either lift-off technique or nickel plating by using the fabricated resist pattern. It is found that the FEA with a 0.3mum gap fabricated by the lift-off technique works from an operating voltage of 30V.The FEA with a 0.8mum gap fabricated by the nickel plating works from a voltage of 110V.(ii) Fabrication of high density vertical silicon emitters.Very fine resist gratings are fabricated with holographic lithography. A dots pattern can be obtained by applying a double exposure in the holographic lithography. The second exposure is done after the sample is rotated by 90ﾟ. The pattern of dots with a 0.2mum diameter and a 0.5mum period is obtained within the area of 2mm square. The density of dots is estimated as 4*10^6mm^<-2>. When a silicon substrate with the dots resist pattern is etched by CF_4 plasmas, a silicon emitter pattern with a high aspect ratio is obtained. However, the top of the emitter is not sharp. We are planing to make sharp emitters by improving the plasma etching condition and/or applying the oxidation for sharpening.In a further study we think it will be possible to improve the fabrication process of lateral nickel FEAs which work at lower voltages and establish the fabrication process of vertical silicon FEAs.

研制一种工作在低电压、高电流密度下的场致发射体阵列（FEA）具有重要意义。发射极和栅极之间的差距以及发射极曲率半径都必须做得很小，以便降低工作电压。为了获得高电流密度，必须增加发射极密度。进行以下实验以开发这种新颖的FEA。(i)由于精细的抗蚀剂图案必须以高分辨率制造，因此我们使用具有1.25的高数值孔径的油浸透镜的光学投影光刻。镍FEAs的制作通过剥离技术或镀镍通过使用制造的抗蚀剂图案。结果表明，采用剥离技术制备的0.3 μ m间隙的FEA在30 V的工作电压下工作，采用镀镍技术制备的0.8 μ m间隙的FEA在110 V的工作电压下工作。(ii)高密度垂直硅发射极的制作用全息光刻法制作了非常精细的抗蚀剂光栅。在全息照相平版印刷术中，通过施加双重曝光可以获得点图案。在样品旋转90 °后进行第二次曝光。在2平方毫米的面积内获得了直径为0.2 μ m、周期为0.5 μ m的点的图案。点的密度估计为4*10^6mm^<-2>。用CF_4等离子体刻蚀带有点抗蚀剂图形的硅衬底，得到了高深宽比的硅发射极图形。然而，发射器的顶部并不尖锐。我们正计划通过改善等离子体刻蚀条件和/或应用氧化来锐化来制造尖锐的发射极。在进一步的研究中，我们认为有可能改进工作在较低电压下的横向镍FEAs的制造工艺，并建立垂直硅FEAs的制造工艺。