Multi-Level Circuit Simulator Using Hardware Description Language

本研究分别于1996年和1971年将模拟硬件描述语言MAST-AHDL与ASSIST系统结合开发电路模拟器，开发了模拟/数字混合信号模拟器SPADE；开发了能够处理集总/分布元件混合电路的多级模拟器DESIRE；开发了一种新型高速神经网络模拟器。1998年，上述研究继续进行，得到了以下结果：a)模拟硬件描述语言verilog - a已与ASSIST相结合。因此，我们构建了能够使用Verilog-A对功能块进行建模的系统，其中SPADE可以模拟混合信号电路。)扩展的GMC已被提出用于大规模互连网络分析。并将时域有限差分法与DESIRE相结合。因此，我们构建了高性能模拟器，可以有效地模拟具有许多互连的线性/非线性大型网络。c)我们将SPADE应用于神经网络的仿真，其中运算放大器和神经元放大器已由Verilog-A建模。结果表明，模拟神经网络可以通过SPADE进行有效的仿真。

In this research, in 1996 and 19971)Combination of the analog hardware description language MAST-AHDL with the system ASSIST for development of circuit simulators, and development of the analog/digital mixed signal simulator SPADE,2) Development of the multi-level simulator DESIRE which can cope with lumped/distributed elements-mixed circuits,3)Development of a novel high-speed neural network simulator have been done. in 1998, the above researches has been continued and the following results have been obtained.a)The analog hardware description language Verilog-Ahas been combined with ASSIST.As a result, we have constructed the system which enables modeling of the functional blocks by Verilog-A, where SPADE can simulate the mixed signal circuitsb)The expanded GMC has been proposed for the large scale interconnect network analysis. Furthermore, FDTD method has been combined with DESIRE.As a result, we have constructed the high performance simulator which can simulate efficiently linear/nonlinear large networks with many interconnects.c) We have applied SPADE to the simulation of neural networks, where the operational amplifier and the neuron amplifier have been modeled by Verilog-A.As a result, we have confirmed that analog neural networks can be simulated efficiently by SPADE.