Multi-Level Circuit Simulator Using Hardware Description Language

使用硬件描述语言的多级电路模拟器

• 批准号: 08650461
• 负责人: ASAI Hideki
• 金额: $ 1.6万
• 依托单位: Shizuoka University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 1996
• 资助国家: 日本
• 起止时间: 1996 至 1998
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08650461/
• 关键词: Hardware description language; Multi-level circuit simulator; Transmission line simulator; Analog; digital mixed circuit; Verilog-A; Neural network; Verilog・A; デジタル混合信号; 波形緩和; ウィンドウ分割技法; 動作記述; 混合信号シミュレーション; マルチレベルシミュレーション

In this research, in 1996 and 19971)Combination of the analog hardware description language MAST-AHDL with the system ASSIST for development of circuit simulators, and development of the analog/digital mixed signal simulator SPADE,2) Development of the multi-level simulator DESIRE which can cope with lumped/distributed elements-mixed circuits,3)Development of a novel high-speed neural network simulator have been done. in 1998, the above researches has been continued and the following results have been obtained.a)The analog hardware description language Verilog-Ahas been combined with ASSIST.As a result, we have constructed the system which enables modeling of the functional blocks by Verilog-A, where SPADE can simulate the mixed signal circuitsb)The expanded GMC has been proposed for the large scale interconnect network analysis. Furthermore, FDTD method has been combined with DESIRE.As a result, we have constructed the high performance simulator which can simulate efficiently linear/nonlinear large networks with many interconnects.c) We have applied SPADE to the simulation of neural networks, where the operational amplifier and the neuron amplifier have been modeled by Verilog-A.As a result, we have confirmed that analog neural networks can be simulated efficiently by SPADE.

本研究于1996年和1997年1）将模拟硬件描述语言MAST-AHDL与系统ASSIST相结合，开发了模拟/数字混合信号模拟器SPADE; 2）开发了可科普集总/分布元件混合电路的多级模拟器SPINRE; 3）开发了一种新型的高速神经网络模拟器。1998年，我们继续进行了上述研究，并取得了以下成果：a）将模拟硬件描述语言Verilog-A与ASSIST相结合，构建了一个能够用Verilog-A对功能块进行建模的系统，其中SPADE可以模拟混合信号电路; b）提出了用于大规模互连网络分析的扩展GMC。将时域有限差分法（FDTD）与时域有限差分法（EFDRE）相结合，构造了一个高性能的模拟器，可以有效地模拟具有多个互连点的线性/非线性大型网络。c）将SPADE应用于神经网络的模拟，其中运算放大器和神经元放大器采用Verilog-A建模，结果表明SPADE可以有效地模拟模拟神经网络。

项目成果

Atsushi Kamo: "Transient Analysis for Transmission Line Networks Using Expanded GMC" Proc.int'l Symp.on Nonlinear Theory and its Applications. 1. 263-266 (1998)

Atsushi Kamo：“使用扩展 GMC 进行传输线网络的瞬态分析”Proc.intl Symp.on 非线性理论及其应用。

Takayuki Watanabe: "Transient Analysis for High-Speed Interconnect Networks Based on AWE and Delay Evaluation Technique" Proc.IEEE Int'l Conf.on Electronics, Circuits and Systems. vol.3 of 3. 103-106 (1998)

Takayuki Watanabe：“基于 AWE 和延迟评估技术的高速互连网络瞬态分析”Proc.IEEE 国际电子、电路和系统会议。

Atsushi Kamo: "Neural Network Simulator for Spatiotemporal Pattern Analysis" Proc.IEEE Int'l Conf.on Electronics,Circuits and Systems. 2of3. 109-112 (1998)

Atsushi Kamo：“用于时空模式分析的神经网络模拟器”Proc.IEEE 国际电子、电路和系统会议。

吉見 勤: "Spiceとの互換を目指した回路シミュレータ開発支援ツールASSISTの改良" 電子情報通信学会技術研究報告. CAS98(発売予定). (1999)

Tsutomu Yoshimi：“改进 ASSIST，一种旨在与 Spice 兼容的电路模拟器开发支持工具”IEICE 技术研究报告（计划发布）。

T.Watanabe: "DESIRE3T+ : Waveform Relaxation-Based Simulator for Coupled Lossy Transmission Lines Circuits" Proc.IEEE Int'l Conf.on Electronics,Circuits and Systems. Vol.1. 370-373 (1996)

T.Watanabe：“DESIRE3T：用于耦合有损传输线电路的基于波形松弛的模拟器”Proc.IEEE 国际电子、电路和系统会议。