Advanced Parallel Digital Signal Processing By Using Complex and Hyper-Complex Systems

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The aim of this study is the realization of advanced parallel digital signal processing systems by using complex and hyper-complex coefficient circuits. This study has studied this theme for four years, and obtained following results. A realization of real-coefficient circuits on a complex digital signal processor is proposed. This is a new application of such a processor. The evaluation of its performance is also given. The proposed method is effective to realize such structures that included adders have more than two input branches. An implementation method of the above method on already proposed complex digital signal processor PSI is studied. A new processing mode named "advance mode" is introduced as an improvement of PSI in order to reduce the overhead of real processing. This study also proposes a new structure of complex multipliers with extended input buses. To evaluate the performance of the advance mode, a hardware simulator is developed. It is well known that complex processing units with redundant arithmetics can realize highspeed complex circuits because they have no carry propagation. However, this study shows that the conventional complex units cannot implement real circuits in the advance mode effectively. This study proposes a new complex redundant binary arithmetic suitable for the advance mode. Two types of partial product selectors based this arithmetic are derived.