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Advanced Parallel Digital Signal Processing By Using Complex and Hyper-Complex Systems

使用复杂和超复杂系统的高级并行数字信号处理

基本信息

批准号：
10650378
负责人：
WATANABE Eiji
金额：
$ 2.11万
依托单位：
Shibaura Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-10650378/
关键词：
Digital Signal Processor Complex Signal Processing Digital Signal Processing Tranfer Function Circuit Synthesis Digital Filter Prallel Processing Discrete-Time System

项目摘要

The aim of this study is the realization of advanced parallel digital signal processing systems by using complex and hyper-complex coefficient circuits. This study has studied this theme for four years, and obtained following results. A realization of real-coefficient circuits on a complex digital signal processor is proposed. This is a new application of such a processor. The evaluation of its performance is also given. The proposed method is effective to realize such structures that included adders have more than two input branches. An implementation method of the above method on already proposed complex digital signal processor PSI is studied. A new processing mode named "advance mode" is introduced as an improvement of PSI in order to reduce the overhead of real processing. This study also proposes a new structure of complex multipliers with extended input buses. To evaluate the performance of the advance mode, a hardware simulator is developed. It is well known that complex processing units with redundant arithmetics can realize highspeed complex circuits because they have no carry propagation. However, this study shows that the conventional complex units cannot implement real circuits in the advance mode effectively. This study proposes a new complex redundant binary arithmetic suitable for the advance mode. Two types of partial product selectors based this arithmetic are derived.

本研究的目的是利用复数和超复数系数电路实现先进的并行数字信号处理系统。本研究对这一主题进行了四年的研究，取得了以下成果。提出了一种在复数数字信号处理器上实现实系数电路的方法。这是这种处理器的新应用。并对其性能进行了评价。该方法能有效地实现包含加法器具有两个以上输入支路的结构。研究了上述方法在已提出的复数数字信号处理器PSI上的实现方法。为了减少实时处理的开销，在PSI的基础上引入了一种新的处理模式--“高级模式”。本研究还提出了一种具有扩展输入总线的复数乘法器的新结构。为了评估先进模式的性能，开发了一个硬件模拟器。众所周知，具有冗余运算的复数处理单元可以实现高速复杂电路，因为它们没有进位传播。然而，这项研究表明，传统的复数单元不能有效地在高级模式下实现真实电路。本研究提出了一种新的适用于高级模式的复数冗余二进制算法。给出了基于该算法的两种部分乘积选择器。