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A Study on Hardware Implementation of a Genetic Algorithm with Adaptive Parameter Adjustment

自适应参数调整遗传算法的硬件实现研究

基本信息

批准号：
10680356
负责人：
WAKABAYASHI Shinichi
金额：
$ 2.11万
依托单位：
Hiroshima University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 1999
项目状态：
已结题

项目摘要

The aim of this research is to develop a genetic algorithm (GA), which is able to adjust the values of genetic parameters during the algorithm execution, and is suitable for hardware implementation.In 1998, we developed a GA hardware called GAA-II, which selected the crossover operators and mutation rates based on the superiority of an individual. GAA-II can be used as a stand-alone core processor of a hardware GA system. It can also be used to implement a parallel GA by connecting a set of GAA-II chips. GAA-II was designed with the Verilog hardware description language, and implemented as an LSI chip in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo. Compared with the ordinary software GA, GAA-II runs 20 to 50 times faster than that to get the same results.In 1999, we developed an evaluation board to evaluate the GAA-II chip. From the experiments with the evaluation board, it was confirmed that the basic functions of the GAA-II chip were correctly implemented. As an extension of GAA-II, we also investigated a parallel GA, which had a function of adaptive parameter adjustment, and was based on a hierarchical population model. In this parallel GA, GA parameters were exchanged among subpopulations during the GA execution to obtain good results in a short computation time. Experimental results showed the effectiveness of the proposed adaptive parallel GA.Results obtained in this research were presented in several international and domestic conferences and workshops, and published as journal papers. From this research, many fruitful results have been obtained, which will be useful for future research on genetic algorithms and their hardware implementation.

本研究的目的是开发一种遗传算法（GA），它能够在算法执行过程中调整遗传参数的值，并适合于硬件实现。在1998年，我们开发了一个GA硬件称为GAA-II，它选择的交叉算子和变异率的基础上，一个个体的优势。GAA-II可作为硬件GA系统的独立核心处理器。它也可以用来实现一个并行GA通过连接一组GAA-II芯片。GAA-II是用Verilog硬件描述语言设计的，并在东京大学VLSI设计与教育中心（VDEC）的芯片制造计划中作为LSI芯片实现的。与普通的软件GA相比，GAA-II的运行速度要快20 ~ 50倍。通过对评估板的实验，确认GAA-II芯片的基本功能得到了正确实现。作为GAA-II的扩展，我们还研究了一种基于分层种群模型的具有自适应参数调整功能的并行遗传算法。在这种并行遗传算法中，遗传参数之间交换的子种群在遗传算法执行过程中，以获得良好的结果，在较短的计算时间。实验结果表明，所提出的自适应并行遗传算法的有效性。在这项研究中取得的成果，在一些国际和国内的会议和研讨会，并发表在期刊论文。本文的研究工作取得了丰硕的成果，为遗传算法的进一步研究及其硬件实现提供了有益的参考。