A study on VLSI layout methods based on meta-heuristics

点击翻译按钮获取中文摘要

In this research, we have studied the VLSI layout design methods based on meta-heuristics. For all algorithms developed in this research, we have performed simulations experiments to show their effectiveness. Summaries of the research results are as follows.1.Hypergraph partitioning algorithms : We have developed algorithms for the hypergraph partitioning problem, which is one of the fundamental problems in VLSI layout design. In the proposed algorithms, clustering of nodes is performed to get a good solution.2.A floorplanning method based on topological constraint manipulation : For the floorplan design of VLSI chips, we have developed a floorplanning algorithm, in which topological constraints of block placement arre dynamically changed.3.Cell placement algorithms : We have developed two cell placement algorithms, one of which is based on genetic algorithms, and the other is a timing-driven cell placement algorithm.4.Global routing methods : We have developed two global routing methods for standard cell layouts, whose objective is to minimize both the channel density and the total wire length.5.Over-the-cell channel routing methods : We have proposed new cell models for standard cell layout design with over-the-cell three-layr channel routing, and developed channel routing algorithms.