Research on Code Generation Algorithms for Retargetable Compilers for DSPs

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In this project, we conducted a research on code generation problem for retargetable compilers for DSPs (digital signal processors). We formalized a code generation problem, developed algorithms to solve this problem, and developed a prototype compiler based on the algorithms.The task of code generation consists of three phases : 1) instruction selection, 2) binding, and 3) scheduling. As for 1), we developed a rule based method of rewriting dataflow graphs. As for 2) we developed a heuristic algorithm to minimize the number of the additional data transfer operations and yet to maximize the parallelism among operations. As for 3), we solved the difficulty with respect to the register capacity constraints by introducing a register constraints analysis phase before list-based scheduling. We also proposed an analysis method of minimizing spill codes.We implemented a prototype compiler by which we compiled a G.723.1 speech codec program written in C language, targeting various datapath configuration with differenet numbers of MAC units or different bus configurations. It was found that we can observe the trade-off between the hardware costs and the number of execution cycles.