Research on retargetable code generation for custom VLIW DSPs

在这个项目中，我们试图为大阪大学开发的ASIP-Meister处理器综合系统开发一个可重定向的编译器，并设计新的代码调度算法，以期建立一种高效的可重定向编译方法。我们研究了ASIP-Meister系统的处理器规范语言和底层VLIW处理器模型，以设计一种称为操作表的数据结构，该结构总结了可重定向代码生成所需的处理器信息。主要的技术贡献之一是一种从指令集的行为描述生成一组指令模式的方法，其中自动生成编译器所必需但在说明书中未明确描述的指令模式。另一个贡献是从处理器规范中提取操作延迟。对于所有RAW、WAR和WAW依赖项，我们开发了一种在存在流水线转发的情况下计算操作延迟的方法。对于代码调度算法，重点研究了基于符号状态遍历和布尔可满足性的精确调度方法。除了扩展这些方法以便处理多周期和流水线计算单元之外，我们还开发了一个使用伪布尔可满足性求解器的框架。它可以直接处理伪布尔约束，即线性不等式，从而有助于加速代码生成。

In this project, we have attempted to develop a retargetable compiler for "ASIP Meister" processor synthesis system, which have been developed at Osaka University, and to design new algorithms for code scheduling, with a view to establish an efficient retargetable compilation method.We examined the processor specification language and the underlying VLIW processor model of the ASIP-Meister system, so as to design a data structure called an operation table which summarizes the processor information necessary for retargetable code generation. One of the major technical contributions is a method of generating a set of the instruction patterns from behavioral description of the instruction set, in which instruction patterns that are necessary for compilers but are not explicitly described in the specification are automatically generated. Another contribution is extraction of the operation latencies from processor specifications. We have developed a method of computing operation latencies in the presence of pipeline forwarding, for all the RAW, WAR, and WAW dependencies. This is based on a way of specifying forwarding using forwarding units and formalization of correct and complete forwarding.As for a code scheduling algorithm, we focused on exact methods based on symbolic state traversal and Boolean satisfiability. As well as extending those methods so that multicycle and pipelined computation units can be handled, we have developed a framework of using a pseudo-Boolean satisfiability solver. It can directly deal with pseudo-Boolean constraints, i.e.linear inequalities, and thus contributes to speeding up of code generation.