Research on Control Dominant High-Level Synthesis

在这个项目中，我们对一种高级合成方法进行了研究，该方法试图合成低成本的高性能电路，用于控制主导应用，如调制解调器，音频压缩/解压缩系统和视频压缩/解压缩系统。我们开发了一个合成系统的原型。它以C语言子集编写的行为规范作为输入，生成寄存器传输级VHDL代码。利用本研究组现有的逻辑合成系统和自动布局系统，可以将VHDL代码进一步转换为VLSI版图。应用该系统合成了椭圆滤波器、空气边缘检测滤波器和部分MPEG音频处理器等电路。该程序的CPU效率很高，但我们发现用于数据传输和控制电路的电路趋于变大。作为解决这个问题的一种方法，我们尝试了一种方法，其中设计者给出数据路径配置，即功能单元及其连接，合成器生成控制电路。在这个方案中，我们发现绑定，即将给定程序中的操作分配给功能单元的任务，成为一个关键。我们开发了两种算法来有效地解决这个问题。我们假设对合成电路采用VLIW型控制，其中控制存储器的大小成为一个问题。我们开发了一种基于控制字的字段分区来减少所需内存大小的算法。

In this project, we conducted a research on a high-level synthesis method which attempts to synthesize low-cost high-performance circuits for control dominant applications, such as modems, audio compression/decompresson systems, and video compression/decompression sys-tems.We developed a prototype of a synthesis system. It takes, as an input, a behavioral pecification written in a subset of C language and generates an register transfer level VHDL code. The VHDL code can be further converted into VLSI layout using logic synthesis system and automatic layout system available in our research group. We applied our system to synthesize a number of circuits including an elliptic filter, air edge detection filter, and a part of MPEG audio processor. The program is CPU efficient but we found that circuits for data transfer and control circuits tend to become large.As one way of resolving this problem, we tried an approach in which designer gives datapath configuration, i.e. functional units and their connectivity, and synthesizer generates control circuits. In this scheme we found that of binding, a task of assigning operations in the given program to functional units, becomes a key. We developed two algorithms to solve this problem efficiently.We assume a VLIW type control for the synthesized circuits, in which the size of the control memory becomes a problem. We developed an algorithm to reduce the necessary memory size based on field partition on the control words.