Automatic Cross-Layer Synthesis of High Performance, (Ultra-)Low Power Hardware Implementations from Data Flow Specifications by Integration of Emerging FeFET Technology

通过集成新兴 FeFET 技术，根据数据流规范自动跨层综合高性能、（超）低功耗硬件实现

• 批准号: 530178246
• 负责人: Dr.-Ing. Joachim Falk
• 金额: --
• 依托单位: Institut des Nanotechnologies de Lyon (INL)
• 依托单位国家: 德国
• 项目类别: Research Grants
• 资助国家: 德国
• 项目状态: 未结题
• 来源: https://gepris.dfg.de/gepris/projekt/530178246?language=en
• 关键词: Automatic; Cross; Layer; Synthesis; Performance

High throughput data and signal processing applications can be specified preferably by dataflow networks, as these naturally allow the exploitation of parallelism as well globally (at the level of a network of communicating actors) as locally at the actor level, e.g., by implementing each actor as a hardware circuit. Now, there exist a few system-level design approaches today to aid an algorithm designer in compiling a dataflow network to a set of processors or, alternatively, to synthesize the network directly in hardware for achieving high processing speeds. But embedded systems, particularly in the context of IoT applications, have additional requirements: Safe operation, even in an environment of intermittent power shortages, and in general (ultra-)low power requirements. Altogether, these requirements seem to be contradictory. Our proposed project named HiLoDa (High performance, (ultra-Low) power Dataflow) Nets tries to attack the obvious discrepancy and conflict in requirements by a) introducing, exploiting, and integrating for the first time emerging FeFET technology for the design of actor networks, i.e., by investigating and designing persistable FIFO-based memory units. b) In particular, circuit devices being able to operate in mixed volatile/non-volatile mode of operation shall be modeled, characterized, and designed. c) By combining the system-level concept of dataflow, which is based on self-scheduled activations of computations with emerging CMOS-compatible FeFET technology, inactive actors or even subnets shall inherit the capability of self-powering (down and wakeup). In addition, for a continuously safe mode of operation, a down-powering must also be triggered upon any intermittent shortage of power supply. Analogously, actors shall perform an auto-wakeup after recovery from a power shortage but also subject to fireability. HiLoDa Nets will be able to combine high clock-speed data processing of each synthesized actor circuit in power-on mode and automatic state retention using FeFET technology in power-off mode, self-triggered during time intervals of either data unavailability or power shortage. d) A fully automatic cross-layer synthesis from system-level dataflow specification to optimized circuit implementation involving FeFET devices shall be developed. This includes e) the DSE (design space exploration) of actor clusterings at the system level to explore individual power domains for the optimization of throughput, circuit cost, energy savings, and endurance. Finally, f) HiLoDa Nets shall be compared to conventional CMOS technology implementations with respect to energy consumption for applications such as spiking neural networks. Likewise, shutdown (backup) and recovery latencies from power shortages shall be evaluated and optimized.

高吞吐量数据和信号处理应用程序最好由数据流网络指定，因为这些自然允许在全局（在通信参与者网络级别）以及在参与者级别本地利用并行性，例如，通过将每个动作器实现为硬件电路。现在，存在一些系统级设计方法，以帮助算法设计者将一个并行网络编译成一组处理器，或者直接在硬件中合成网络以实现高处理速度。但嵌入式系统，特别是在物联网应用的背景下，有额外的要求：安全运行，即使在间歇性电力短缺的环境中，以及一般（超）低功耗要求。总之，这些要求似乎是相互矛盾的。我们提出的名为HiLoDa（高性能，（超低）功率数据流）Nets的项目试图通过以下方式解决需求中的明显差异和冲突：a）首次引入，开发和集成新兴的FeFET技术用于演员网络的设计，即，通过研究和设计基于FIFO的持久性存储单元。B）特别地，应当对能够以混合易失性/非易失性操作模式操作的电路器件进行建模、表征和设计。c）通过将基于计算的自调度激活的系统级概念与新兴的CMOS兼容FeFET技术相结合，不活动的参与者或甚至可编程逻辑器件将继承自供电（关闭和唤醒）的能力。此外，对于持续安全的操作模式，还必须在任何间歇性的电力供应不足时触发断电。类似地，演员将在从电力短缺恢复后执行自动唤醒，但也受可射击性的影响。HiLoDa Nets将能够在上电模式下联合收割机每个合成演员电路的高时钟速度数据处理，并在断电模式下使用FeFET技术自动保持状态，在数据不可用或电力短缺的时间间隔内自触发。d）应开发从系统级低功耗规范到涉及FeFET器件的优化电路实现的全自动跨层综合。这包括e）在系统级的参与者集群的DSE（设计空间探索），以探索各个功率域，以优化吞吐量、电路成本、节能和耐久性。最后，f）HiLoDa网络将与传统CMOS技术实现方式在诸如尖峰神经网络等应用的能耗方面进行比较。同样，应评估和优化电源短缺的关机（备份）和恢复延迟。