Automatic Cross-Layer Synthesis of High Performance, (Ultra-)Low Power Hardware Implementations from Data Flow Specifications by Integration of Emerging FeFET Technology

高吞吐量数据和信号处理应用程序可以优选地由数据流网络指定，因为这些自然地允许利用并行性，以及全局（在通信参与者网络级别）和本地参与者级别，例如，通过将每个参与者实现为硬件电路。现在，存在一些系统级设计方法来帮助算法设计者将数据流网络编译为一组处理器，或者直接在硬件中合成网络以实现高处理速度。但是嵌入式系统，特别是在物联网应用的背景下，有额外的要求：即使在间歇性电力短缺的环境中也能安全运行，并且通常（超低）功耗要求。总之，这些要求似乎是相互矛盾的。我们提出的项目HiLoDa（高性能，（超低）功耗数据流）网试图通过a)首次引入，开发和集成用于actor网络设计的新兴FeFET技术来解决需求中的明显差异和冲突，即通过研究和设计可持久的基于fofo的存储单元。b)特别是，能够在易失性/非易失性混合工作模式下工作的电路器件应进行建模、表征和设计。c)将基于自调度激活计算的系统级数据流概念与新兴的cmos兼容FeFET技术相结合，使非活动参与者甚至子网继承自上电（关机和唤醒）的能力。此外，为了实现连续安全运行模式，还必须在任何间歇性电源短缺时触发下电。类似地，参与者在从电力短缺中恢复后应执行自动唤醒，但也受可火性的影响。HiLoDa Nets将能够在上电模式下结合每个合成元件电路的高时钟速度数据处理，并在断电模式下使用ffet技术自动保持状态，在数据不可用或电力短缺的时间间隔内自动触发。d)应开发从系统级数据流规范到涉及ffet器件的优化电路实现的全自动跨层综合。这包括e)系统级参与者聚类的DSE（设计空间探索），以探索单个功率域，以优化吞吐量、电路成本、节能和耐用性。最后，f) HiLoDa Nets应与传统CMOS技术实现在诸如尖峰神经网络等应用的能耗方面进行比较。同样，断电（备份）和恢复延迟也要进行评估和优化。

High throughput data and signal processing applications can be specified preferably by dataflow networks, as these naturally allow the exploitation of parallelism as well globally (at the level of a network of communicating actors) as locally at the actor level, e.g., by implementing each actor as a hardware circuit. Now, there exist a few system-level design approaches today to aid an algorithm designer in compiling a dataflow network to a set of processors or, alternatively, to synthesize the network directly in hardware for achieving high processing speeds. But embedded systems, particularly in the context of IoT applications, have additional requirements: Safe operation, even in an environment of intermittent power shortages, and in general (ultra-)low power requirements. Altogether, these requirements seem to be contradictory. Our proposed project named HiLoDa (High performance, (ultra-Low) power Dataflow) Nets tries to attack the obvious discrepancy and conflict in requirements by a) introducing, exploiting, and integrating for the first time emerging FeFET technology for the design of actor networks, i.e., by investigating and designing persistable FIFO-based memory units. b) In particular, circuit devices being able to operate in mixed volatile/non-volatile mode of operation shall be modeled, characterized, and designed. c) By combining the system-level concept of dataflow, which is based on self-scheduled activations of computations with emerging CMOS-compatible FeFET technology, inactive actors or even subnets shall inherit the capability of self-powering (down and wakeup). In addition, for a continuously safe mode of operation, a down-powering must also be triggered upon any intermittent shortage of power supply. Analogously, actors shall perform an auto-wakeup after recovery from a power shortage but also subject to fireability. HiLoDa Nets will be able to combine high clock-speed data processing of each synthesized actor circuit in power-on mode and automatic state retention using FeFET technology in power-off mode, self-triggered during time intervals of either data unavailability or power shortage. d) A fully automatic cross-layer synthesis from system-level dataflow specification to optimized circuit implementation involving FeFET devices shall be developed. This includes e) the DSE (design space exploration) of actor clusterings at the system level to explore individual power domains for the optimization of throughput, circuit cost, energy savings, and endurance. Finally, f) HiLoDa Nets shall be compared to conventional CMOS technology implementations with respect to energy consumption for applications such as spiking neural networks. Likewise, shutdown (backup) and recovery latencies from power shortages shall be evaluated and optimized.