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Design of highly reliable circuit considering crosstalk noise

考虑串扰噪声的高可靠电路设计

基本信息

批准号：
18500040
负责人：
MIURA Yukiya
金额：
$ 0.86万
依托单位：
Tokyo Metropolitan University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2006
资助国家：
日本
起止时间：
2006 至 2007
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-18500040/
关键词：
Crosstalk Dependable design Synchronous circuits Edge trigger clock Level sensitive clock Self-correction Periodic signal

项目摘要

In order to guarantee proper function of a system,a correct clock signal must be distributed. A crosstalk noise induced by a parasitic capacitance between signal lines gives a large influence to a digital circuit. This influence is called a crosstalk fault. Moreover,since synchronous digital circuits are the dominant technology in the present day,it is possible to cause incorrect behavior in many parts in the circuit when the crosstalk noise is generated on the clock signal line. It is difficult to eliminate perfect causes of crosstalk noises. Moreover,crosstalk noises are not always detected as faults,because their influence may cause behavior of intermittent faults and crosstalk noises happen accidentally by unintended causes. In this work,we proposed two methods for distributing the clock signal that take account of crosstalk noises generated on the clock signal line,which are applicable to conventional synchronous digital systems. For the clock signal of a pulse type,we proposed a double/multiple clock pulse method that has the tolerance for an incorrect clock pulse induced by a crosstalk fault. For the clock signal of a level sensitive type,we proposed a self-correction method for the change of the clock signal width during system operation. The proposed method does not require a reference signal for signal correction. The circuits implemented by both methods can be inserted into clock signal.lines as adapter circuits for the conventional clocked element and flip-flop,and as a result,the proposed methods are easily built in conventional synchronous digital circuits. From simulation results,we find that implemented circuits had the ability of the tolerance for the process variations. Two proposed methods are applicable to not only LSIs but also every synchronous circuit including board circuits. Besides,they are useful for circuits demanding high reliability.

为了保证系统的正常工作，必须分配正确的时钟信号。由信号线间寄生电容引起的串扰噪声对数字电路有很大的影响。这种影响被称为串扰故障。此外，由于同步数字电路是当今的主导技术，当时钟信号线上产生串扰噪声时，可能会导致电路中许多部分的不正确行为。很难完全消除产生串声噪声的原因。此外，由于串扰噪声的影响可能导致间歇性故障的行为，串扰噪声也可能因意外原因而意外发生，因此串扰噪声并不总是被检测为故障。在这项工作中，我们提出了两种适用于传统同步数字系统的时钟信号分配方法，这些方法考虑了时钟信号线上产生的串扰噪声。对于脉冲类型的时钟信号，我们提出了一种双/多时钟脉冲方法，该方法对串扰故障引起的错误时钟脉冲具有容忍度。针对电平敏感型时钟信号，提出了一种针对系统运行过程中时钟信号宽度变化的自校正方法。该方法不需要参考信号进行信号校正。两种方法实现的电路都可以插入时钟信号。线路作为传统时钟元件和触发器的适配器电路，因此，所提出的方法很容易构建在传统的同步数字电路中。仿真结果表明，所实现的电路具有对工艺变化的容忍能力。这两种方法不仅适用于lsi，而且适用于包括电路板电路在内的所有同步电路。此外，它们对要求高可靠性的电路也很有用。