Memory-based VLSI brain research for realizing recognition, learning and decision capability

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Algorithms, architectures and integrated-circuits of functional-core units for an associative-memory-based VLSI brain were developed. Additionally, actual VLSI test-chips were designed and measured. A 180nm CMOS test chip of the "knowledge-pattern storage and nearest-distance search" unit achieved 50-245ns search time, <36.5mW power consumption and >99% positive detection rate. The developed algorithms and integrated circuits for realizing the "winner readout and recognition decision", "patterns learning" and "pattern optimization" units are based on the concepts of a recognition threshold, short/long term storage and reference-pattern updates derived from the previously recognized input patterns. We selected "handwritten character recognition" as a representative application for performance evaluation of the developed VLSI brain. With the reference-data-optimization algorithms, misclassification was reduced from 35% to 9%. A VLSI-brain test chip with automatic hand-written-character learning capability functioned correctly up to 100MHz, completed each reference-pattern learning and optimization step in about 2μs and had a low power consumption of 116mW.