Nano-structure Control of Cu Interconnects by a Very High Purity Plating Processes and Its Application to Next-generation LSIs.

极细铜线（≤ 50nm）的晶粒尺寸及其分布对LSI的器件性能和可靠性有着至关重要的影响。这是因为铜线中的平均晶粒尺寸对于较窄的线变得更小，特别是。非常细的晶粒导致Cu线的电阻率显著增加和可靠性降低。为了降低电阻率，提高可靠性，最终达到提高LSI性能的目的，我们研究了使用高纯度电镀材料和少量添加剂的Cu线的纯化工艺，得到了比使用常规纯度电镀材料制备的Cu线电阻率降低30%以上的Cu线。

Grain sizes and their distribution in very narrow Cu wires (≦50nm) have a crucial influence on device performances and reliabilities of LSIs. This is because the average grain size in Cu wires becomes smaller for narrower wires and especially. Very fine grains causes substantial resistivity increase and reliability degradation of Cu wires. In order to reduce resistivity and raise reliability, with the final goal being to enhance LSI performance, we have investigated the purification process of Cu wires using high-purity plating materials and little additives and gotten Cu wires with more than 30% lower resistivity than those made with conventional purity plating materials.