Development of Cu Interconnects for 20nm Technology Node LSI

20nm 技术节点 LSI 的铜互连开发

基本信息

  • 批准号:
    17206071
  • 负责人:
  • 金额:
    $ 32.53万
  • 依托单位:
  • 依托单位国家:
    日本
  • 项目类别:
    Grant-in-Aid for Scientific Research (A)
  • 财政年份:
    2005
  • 资助国家:
    日本
  • 起止时间:
    2005 至 2007
  • 项目状态:
    已结题

项目摘要

Copper (Cu) has long been used as the wire material for high performance ultra large-scale integrated circuits (ULSIs). However, the significant increase in the resistivity of Cu wire with line widths less than 100 nm is a critical issue^< (1-3)>. In order to lower resistivity, both the coarsening of the grain sizes and the reduction in the thickness of high-resistivity barrier metals in Cu wires are crucial. However, a powerful grain size coarsening process to reduce electron scattering has not yet been developed up to now. It was recently reported that contamination in Cu films depress their grain growth during annealing^< (6)>.This implies that low resistivity Cu wires could be created if high-purity very narrow wires can be formed. Hence, we have focused our attention on the purification of Cu wires and the investigation of a forming process using ultra-high purity 9N-Cu anode and high purity 6N-CuSO_4・5H_2O electrolyte.Using the above high purity process, we have realized 50 nm wide Cu wires with about 21% lower resistivity than those made with the conventional process. It was also found that the low resistivity Cu wires formed with the new process have large grain sizes with a lower spread, and a much smaller amount of oxygen than those made with the conventional process.
铜长期以来一直被用作高性能超大规模集成电路(ULSI)的布线材料。然而,线宽小于100 nm的铜线的电阻率显著增加是一个关键问题。为了降低铜丝的电阻率,粗化晶粒度和减小高阻金属的厚度是至关重要的。然而,到目前为止,还没有开发出一种有效的减小电子散射的晶粒度粗化过程。最近有报道称,铜膜中的污染抑制了其在退火过程中的晶粒长大。这表明,如果能够形成高纯度的极窄线材,就可以生产出低电阻率的铜线。因此,我们将注意力集中在铜线的提纯和采用超高纯度9N-Cu阳极和高纯度6N-CuSO_4·5H_2O电解液的成形工艺的研究上,采用上述高纯度工艺,我们已经实现了50 nm宽的铜线,其电阻率比传统工艺降低了约21%。研究还发现,与传统工艺相比,采用新工艺生产的低阻铜丝具有较大的晶粒尺寸和较小的扩散,并且含氧量也大大减少。

项目成果

期刊论文数量(48)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Aspect Ratio Dependence of the Resistivity of Fine Line Cu lnterconnects
细线铜互连电阻率与纵横比的关系
  • DOI:
  • 发表时间:
    2007
  • 期刊:
  • 影响因子:
    0
  • 作者:
    K.P.;Khoo・J.;Onuki・T.;Nagano・Y.;Chonan
  • 通讯作者:
    Chonan
これだけは知っておきたい最新の配線・実装技術、特集にあたって
这是您需要了解的有关最新接线和安装技术的全部内容,在此专题中
  • DOI:
  • 发表时间:
    2007
  • 期刊:
  • 影响因子:
    0
  • 作者:
    T.;Akabane・Y.;Sasajima・J.;Onuki;大貫 仁
  • 通讯作者:
    大貫 仁
Coatings Adhesion Evaluation by Nanoscaratching Simulation Using the Molecular Dynamic Method
使用分子动力学方法通过纳米划痕模拟评估涂层附着力
  • DOI:
  • 发表时间:
    2007
  • 期刊:
  • 影响因子:
    0
  • 作者:
    大貫 仁・田代 優・K.P.;Khoo;赤羽智明・影山順平・篠嶋妥;T. Akabane. Y. Sasajima and J. Onuki
  • 通讯作者:
    T. Akabane. Y. Sasajima and J. Onuki
Special Issue on Cu Metallization, Experiments using Computer Simulation for ULSI Interconnects Designing
铜金属化特刊,使用计算机模拟进行 ULSI 互连设计的实验
  • DOI:
  • 发表时间:
    2007
  • 期刊:
  • 影响因子:
    0
  • 作者:
    T. Akabane;J. Kageyama and Y. Sasajima
  • 通讯作者:
    J. Kageyama and Y. Sasajima
Observation of Microstructures in the Longitudinal Direction of Very narrow Cu Interconnects
极窄铜互连线纵向微观结构的观察
  • DOI:
  • 发表时间:
    2006
  • 期刊:
  • 影响因子:
    0
  • 作者:
    K. P. Khoo;J. Onuki;T. Nagano;Y. Chonan;H. Akahoshi;T. Tobita M. Chiba;T. Saitou and K. Ishikawa
  • 通讯作者:
    T. Saitou and K. Ishikawa
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ONUKI Jin其他文献

ONUKI Jin的其他文献

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{{ truncateString('ONUKI Jin', 18)}}的其他基金

Nano-structure Control of Cu Interconnects by a Very High Purity Plating Processes and Its Application to Next-generation LSIs.
通过极高纯度电镀工艺控制铜互连的纳米结构及其在下一代大规模集成电路中的应用。
  • 批准号:
    20226014
  • 财政年份:
    2008
  • 资助金额:
    $ 32.53万
  • 项目类别:
    Grant-in-Aid for Scientific Research (S)

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