A Fundamental Study on Hardware Accelerator for SVG

SVG硬件加速器的基础研究

• 批准号: 20500059
• 负责人: YONEDA Tomohiro
• 金额: $ 2.91万
• 依托单位: National Institute of Informatics
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2008
• 资助国家: 日本
• 起止时间: 2008 至 2010
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-20500059/
• 关键词: 非同期式回路設計; SVG; ハードウェア化; 非同期式設計

In this research project, we have investigated a hardware accelerator for SVG, which accepts SVG descriptions as streams, analyzes them directly, and translates them into low-level drawing command sequences based on a concurrent pipelining mechanism. This idea has been implemented as a logic circuit, and it has been functionally tested using a logic simulation tool. Furthermore, in order to decode SVG descriptions efficiently by hardware, a software preprocessor which extracts sets of objects that can be concurrently drawn without affecting the final results has been developed.

在该研究项目中，我们研究了SVG的硬件加速器，该加速器接受SVG描述作为流，直接分析它们并将其转换为基于同时的管道机制的低级绘图命令序列。这个想法已作为逻辑电路实现，并已使用逻辑模拟工具在功能上进行了测试。此外，为了通过硬件有效地解码SVG描述，该软件是一种软件预处理器，该软件可以提取可以同时绘制而不会影响最终结果的对象集。

项目成果

Asynchronous pipeline controller based on early acknowledgement protocol

• DOI: 10.1109/acsd.2008.4574603
• 发表时间: 2008-06
• 期刊: 2008 8th International Conference on Application of Concurrency to System Design
• 作者: C. Mannakkara;T. Yoneda