A Fundamental Study on Hardware Accelerator for SVG

在这个研究项目中，我们研究了一个SVG的硬件加速器，它接受SVG描述作为流，直接分析它们，并将它们转换为基于并发流水线机制的低级绘图命令序列。这个想法已经被实现为一个逻辑电路，并使用逻辑仿真工具进行了功能测试。此外，为了通过硬件对SVG描述进行高效解码，开发了一种软件预处理器，在不影响最终结果的情况下提取可并发绘制的对象集。

In this research project, we have investigated a hardware accelerator for SVG, which accepts SVG descriptions as streams, analyzes them directly, and translates them into low-level drawing command sequences based on a concurrent pipelining mechanism. This idea has been implemented as a logic circuit, and it has been functionally tested using a logic simulation tool. Furthermore, in order to decode SVG descriptions efficiently by hardware, a software preprocessor which extracts sets of objects that can be concurrently drawn without affecting the final results has been developed.