Research for a design of high-speed packet switch for next-generation networks

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A new design of high-performance ATM switch, which serves as a switching engine of large capacity routers for next generation networks is described. We have proposed a novel scheduling algorithm for input-queued ATM switches, which reserves transmission time of cells at output ports unlike conventional scheduling algorithms that reserve only present time at output queuem and have shown through simulations that our algorithm can overcome conventional scheduling algorithms such as i SLIP. We have also shown a new design of high-speed switch control circuit for Benes switches, which can replace conventional crossbar switches used in input-queued switches for their reduced switch complexity.