Research on Test Methodology for 3D Integrated SoCs

点击翻译按钮获取中文摘要

The objective of this research is to find efficient methods of test generation and design for testability to achieve high quality and low cost test for 3D integrated SoCs. In this research, I focused attention on temperature during test and test data volume for 3D integrated SoCs. Consequently, I established a test generation method to reduce temperature-variation-induced delay test quality loss and a test cost optimization method that can achieve high quality delay test with low test data volume.