Robustness against delay variations and design optimization for datapath circuits with post silicon timing tuning mechanism

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LSIs suffers variations during fabrication process, and timing fault due to those variations is one of the biggest problems for current and future advanced LSIs. Timing skew tuning after fabrication (Post Silicon Skew Tuning) is a key technology to overcome such timing problem and to draw the best possible performance of individual chip. Register transfer level design optimizations of LSIs with PSST mechanism and skew tuning algorithms together with optimized timing test schedule have been developed in this project.