Theory and design of fault tolerant integrated systems

容错集成系统理论与设计

• 批准号: 09450158
• 负责人: KANEKO Mineo
• 金额: $ 3.58万
• 依托单位: Japan Advanced Institute of Science and Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1997
• 资助国家: 日本
• 起止时间: 1997 至 1999
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09450158/
• 关键词: fault tolerance; reconfiguration; error correction; multi-processor; parallel computation; systolic array; fault detection; diagnosis; multiplication; 故障検出; 故障診断; 並列計算処理; ウエハースケール集積回路; ウエハ-スケール集積回路

The aim of this research project is to establish bases for fault tolerant integrated systems which have the potential to correct errors concurrently and to reconfigure themselves so as to exclude faulty components. The major contributions of this project are summarized in the following.1. On-line fault detection and diagnosis for parallel computing systems : We have proposed graph-theoretic model for analysis and synthesis of algorithm-based fault-tolerance systems. Based on this model, we have developed several checking schemes and operation / checking mapping schemes for single-fault-locatable/double-fault-detectable systems.2. On-line error correctable parallel computing on systolic arrays : Fault tolerant systolic array based on Triple Modular Redundancy in mixed spatial-temporal space has been proposed. In this scheme, not only computations but also communications are multiplicated, and link sharing is necessary to reduce its link complexity. Link sharing scheme which guarantees high reliability and schedulability has been also proposed.3. Reconfiguration for fault tolerant network computing on WSIs : Reconfiguration algorithm for torus networks has been proposed. Necessary and sufficient hardware(interconnection resource) redundancy required for this reconfiguration algorithm has been also investigated.Extension to control-intensive applications and a fusion of on-line correctability and reconfigurability are problems to be tackled in future.

本研究项目的目的是建立容错集成系统的基础，该系统具有同时纠正错误和重新配置自身以排除故障组件的潜力。本项目的主要贡献总结如下：并行计算系统的在线故障检测与诊断：我们提出了基于算法的容错系统分析与综合的图论模型。在此模型的基础上，我们提出了单故障可定位/双故障可检测系统的几种检测方案和运行/检测映射方案。在线纠错收缩阵列并行计算：提出了一种基于混合时空三模冗余的容错收缩阵列。该方案不仅计算量大，而且通信量大，需要链路共享来降低链路复杂度。提出了保证高可靠性和可调度性的链路共享方案。基于wsi的容错网络计算重构：提出了环面网络重构算法。本文还研究了重构算法所需的必要和足够的硬件（互联资源）冗余。向控制密集型应用的扩展以及在线可纠错性和可重构性的融合是未来需要解决的问题。

项目成果

Choon-Sik Park, and Mineo Kaneko: "An Efficient Scheme Based on Extended PDC Graph Model in Synthesizing Fault Tolerant FIR Filter"Proceddings of IEEE International Symposium on Circuits and Systems. Vol.V. 253-256 (2000)

Choon-Sik Park 和 Mineo Kaneko：“基于扩展 PDC 图模型的综合容错 FIR 滤波器的有效方案”IEEE 国际电路与系统研讨会论文集。

Choon-Sik Park,Mineo Kaneko: "Checking Scheme for ABFT Systems Based on Modified PD Graph under an Error Generation/Propagation Model"IEICE Trans.Fundamentals. E82-A・6. 1002-1008 (1999)

Choon-Sik Park、Mineo Kaneko：“错误生成/传播模型下基于修正 PD 图的 ABFT 系统检查方案”IEICE Trans.Fundamentals。1002-1008 (1999)。

Mineo Kaneko: "Scheduling and Reliability Aspects Data Routing in Triplicated TMR Sys-tolic/Multiprocessor Systems" Third International Conference on Massively Parallel Computing Systems. (1998)

Mineo Kaneko：“三重 TMR 系统/多处理器系统中的调度和可靠性方面的数据路由”第三届大规模并行计算系统国际会议。

Choon Sik Park, Mineo Kaneko: "Checking Scheme for ABFT Systems Based on Modified PD Graph under an Error Generation/Propagation Model" Proceedings of ITC-CSCC'98. Vol.II. 1703-1706 (1998)

Choon Sik Park、Mineo Kaneko：“错误生成/传播模型下基于修正 PD 图的 ABFT 系统检查方案”ITC-CSCC98 论文集。

Choon-Sik Park,Mineo Kaneko: "An Efficient Technique for Design of ABFT Systems Based on Modified PD Graph"3rd International Conference on Massively Parallel Computing Systems. (1998)

Choon-Sik Park、Mineo Kaneko：“基于改进的 PD 图的 ABFT 系统设计的有效技术”第三届大规模并行计算系统国际会议。