Development of high-performance public-key cryptographic processors with tamper resistance

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This research project developed a high-performance cryptographic processor with a state-of-the-art tamper resistance capability and its design methodology. More precisely, we designed a processor architecture specified for exponentiation operation which is an integral part of public-key cryptographic operation, and developed an RSA processor highly resistant to side-channel attacks. In addition, we demonstrated the validity of the developed processor through an exhaustive set of experiments on side-channel attacks (i.e., chosen-message power/EM analysis attacks and fault injection attacks) against a prototype implementation of the developed processor. Moreover, we developed an automatic generator which generates RSA processors depending on various design specifications.