Low Power Techniques of Network-on-Chips for Many-core Computer Platforms

在本研究中，我们的目标是为构成IT设备的多核处理器平台，如移动终端和高性能计算机，提供创新的动态低功耗和低延迟的片上网络技术。我们的主要解决方案是：(1)针对流量负载进行优化的低功耗可变管频片上路由器（1 ~ 4个周期）；(2)其动态重构技术；(3)将链路长度限制在6核逻辑长度以内的路由器随机拓扑设计。通过全系统仿真和功率估计验证了其效率。

In this study our objective is to present innovative dynamic low-power and low-latency techniques of network-on-chips for many-core processor platforms that form IT equipments, such as mobile terminals and high-performance computers. Our main solutions are (1) low-power variable pipeline-and-frequency on-chip routers (1 cycle to 4 cycles) optimized to traffic load, (2) its dynamic reconfiguration techniques and (3) random topology design of routers whose link length is limited within 6 core logical length. Their efficiency is confirmed via full-system simulation and power estimation.