A Study of Ultra Low-latency Network-on-Chips using Prediction and Partially Duplications

本研究的目的是开发一种创新的超低延迟互连技术，以实现复杂的单片计算机系统平台，如多核和多核处理器。因此，我们提出并评估了(1)使用预测和部分复制的低延迟路由器体系结构，以及(2)通过路由器间协作进一步减少延迟的拓扑和路由的部分重构技术。这项研究的结果能够通过充分利用系统级研究领域的互连网络技术来降低微系统的延迟，例如传统的PC集群和大规模并行计算机。

The objective of this study is to develop an innovative ultra-low latency interconnect technology in order to achieve a complex single-chip computer-system platform, such as multi-core and many-core processers. We thus proposed and evaluated (1) low-latency router architectures using a prediction and partially duplication, and (2) partially reconfiguration techniques of topology and routing for further reducing the latency with inter-router co-operations. The results of this study enable to reduce the latency of micro-systems by making the best use of the interconnection network techniques in system-level research regions, such as traditional PC clusters and massively parallel computers.