A method of high-level synthesis for multi-cycle transient fault tolerant digital systems

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As the advance in semiconductor technologies, transient faults caused by particle strike have become a matter of concern, and further it is predicted that such faults can span across more than one clock cycle.We proposes a high-level synthesis algorithm for long duration transient fault tolerance. On the basis of the properties of operational units for transient error correction and detection among operations, we present (1) a force-directed scheduling algorithm with the force derived from the estimation of operational units according to the properties of error correction and detection, (2) a binding algorithm aiming at achieving both of correctablility and detectability with minimizing the number of operational units, and (3) a method for synthesizing transient fault tolerant controllers that utilizes the correctability/detectability of datapaths. The proposed algorithm can derive multi-cycle fault tolerant systems with small hardware resources compared with simply-tripled datapaths.