Study on Design Methodology for Reducing Both of Spatial and Temoporal Random Threshold Variation Based on Potential Control of SRAM Cell Terminals

基于SRAM单元端子电位控制的减少空间和时间随机阈值变化的设计方法研究

• 批准号: 23560424
• 负责人: YAMAUCHI Hiroyuki
• 金额: $ 3.33万
• 依托单位: Fukuoka Institute of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2011
• 资助国家: 日本
• 起止时间: 2011 至 2013
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23560424/
• 关键词: SRAM; SRAMマージン解析; 時空間ランダムばらつき; ランダムテレグラフノイズ; ランダムドーパントフラクチュエーション; マージンアシスト回路; コンボリューション; デコンボリューション; RTN; 畳み込み; 逆畳み込み; RDF; 時空間ばらつき; ＲＴＮ; ランダムばらつき; ＳＲＡＭ; Vddのスケーリング; σVtの自己収束; σVtを擬似的に検出; インポータンスサンプリング; VLSI設計手法

The purpose of this study is to provide a new design methodology enabling to detect and reduce the spatial/temporal random variations of the threshold voltage in the field after shipment. This study focuses on :(1) concept design for a feasibility study on detection and reduction of the Vt temporally dynamic shift due to Random Telegraph Noise(RTN) (2) physical modeling for the simulation for a feasibility study, and (3) control of offset potential of the terminals of SRAM cell. It has been demonstrated for the first time that the amount of the SRAM overall margin modulation due to the RTN would become unprecedented level and could no longer ignore in the screening design when the tail length of the distribution of the Vt variation for the RTN would exceed that for the random dopant fluctuation (RDF).

本研究的目的是提供一种新的设计方法，能够检测和减少的空间/时间的随机变化的阈值电压在装运后的字段。本研究的重点是：（1）概念设计的可行性研究的检测和减少的Vt的时间动态偏移由于随机电报噪声（RTN）（2）物理建模的仿真可行性研究，和（3）的SRAM单元的端子的偏移电位的控制。首次证明了当RTN的Vt变化分布的尾部长度超过随机掺杂波动（RDF）时，RTN对SRAM总裕度调制的影响将达到前所未有的水平，在屏蔽设计中不能再忽略。

项目成果

A Tech nique to Circumvent V-shaped Deconvolutio n Error for Time-dependent SRAM Margin Analyses

一种避免瞬态SRAM裕度分析中V形反卷积误差的技术

• 发表时间: 2013
• 期刊: IEIE Transactions on Smart Pro cessing and Computing
• 作者: Worawit Somha;Hiroyuki Yamauchi
• 通讯作者: Hiroyuki Yamauchi

FIT 山内研究室

FIT山内实验室

Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device

• DOI: 10.1109/aspdac.2012.6164968
• 发表时间: 2012-03
• 期刊: 17th Asia and South Pacific Design Automation Conference
• 作者: Meng-Fan Chang;C. Chuang;Min-Ping Chen;Lai-Fu Chen;H. Yamauchi;P. Chiu;S. Sheu

A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency

• 发表时间: 2013-06
• 期刊: 2013 Symposium on VLSI Technology
• 作者: Chien-Fu Chen;Ting-Hao Chang;Lai-Fu Chen;Meng-Fan Chang;H. Yamauchi

A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms

• 发表时间: 2011-06
• 期刊: 2011 Symposium on VLSI Circuits - Digest of Technical Papers
• 作者: Meng-Fan Chang;Wei-Cheng Wu;Chih-Sheng Lin;P. Chiu;Ming-Bin Chen;Yen-Huei Chen;H. Lai;Zhe-Hui Lin;S. Sheu;T. Ku;H. Yamauchi