Design and Development of SyMPET: System on chip Modular readout for high-resolution TOF-PET

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PROJECT SUMMARY Nalu Scientific LLC (NSL) proposes to develop and optimize the design of a SiPM-based, low-power, high channel density, waveform-digitizing readout microchip for TOF-PET that will increase image quality and provide more accurate and precise quantization for PET brain imaging, with the potential to significantly improve early diagnosis of neurodegenerative disease while also allowing greater flexibility in the development of personalized patient imaging strategies. NSL’s patented waveform-digitizing “System on Chip” readout ASIC technology has the potential to substantially improve TOF-PET imaging from its current state. During Phase I, we will build on the prior experience and knowledge we have gained using NSL’s technology in developing state-of-the-art high energy and nuclear physics detectors to substantially improve PET imaging readout systems through increased SNR, image contrast and quality, reduced exposure times/dose, and reduced system cost to drive broad acceptance. These improvements will initially focus on brain PET imaging but can be expanded to whole-body systems. We will leverage NSL’s existing portfolio of low-power, low-cost WFD ASIC designs, already proven to work in large particle physics detectors, to implement a PET-specific WFD ASIC optimized for brain PET scanners but equally applicable to whole-body. We will initially develop detailed analytic modeling of light production and transport in scintillating crystals, along with realistic Monte Carlo simulations of sensor and readout electronics in order to derive baseline technical specifications for both a fully optimized TOF-PET WFD readout chip as well as a “bare-bones” implementation substantially based on circuit design elements derived from one or more existing NSL chip designs. NSL’s “System on Chip” WFD architecture, with fully random accessible analog storage, input triggering, and on-chip control capability, allows for a number of highly effective mechanisms to cope with design issues such as e.g., throughput, speed, and buffer length, will be crucial to optimize in the technical specification of a WFC ASIC which meets performance goals while simultaneously fulfilling the stringent constraints on physical and other characteristics such as size, weight, power, and cost that will be required in any realistic TOF-PET system. We will collaborate with Dr. Hamid Sabet (Harvard) to define a realistic full signal chain + readout model and subsequently evaluate its results to generate ASIC technical specifications and architectural design for a substantially improved WFD readout ASIC for TOF-PET systems relative to the current state of the art.