Process Variation Aware Synthesis of Nano-CMOS Circuits

在纳米级CMOS技术发展的背景下，设计工程师的挑战已经增加。设计决策是基于功率的标称值，而性能决策是基于这样的假设，即所有晶体管在管芯和晶圆上都是相似的。然而，实际上，当晶体管相当小时，晶体管参数在管芯之间或甚至在同一管芯中变化。换句话说，管芯或晶片中的每个晶体管是不同的。晶体管参数的变化可能是由于几个因素，包括电介质厚度，衬底，多晶硅和注入杂质水平的变化;表面电荷;和光刻工艺。因此，基于标称模型的设计决策可能是不正确的，因为模型是对实际值的高估或低估;因此，所得电路可能不是最佳的。准确建模和估计所有形式的功率和性能核算过程变化，包括所有泄漏成分，对于正确决策制造设计至关重要。不幸的是，当目标技术是纳米级CMOS时，在数字系统设计期间不存在用于精确估计的综合模型或工具。一些形式的功耗，如由于栅氧化层/结隧穿，没有得到太多的关注。任何（泄漏）电流分量或延迟的过程变化感知建模在系统级处理时具有很大的挑战性。此外，当系统是行为硬件描述语言（HDL）时，不存在可以提供功率性能设计空间探索的工具。在这个项目中提出的研究旨在开发工艺变化意识的架构功耗延迟统计模型和估计器，可用于快速和准确的估计表示为行为HDL的数字系统的纳米级CMOS设计方案的功率性能值。

In the context of development of nanoscale CMOS technology, the challenges for design engineers have increased. Design decisions are based on the nominal values of power, and performance decisions are based on the assumption that all the transistors are alike across dies and wafers. However, in reality, when the transistors are quite small, the transistor parameters vary from die to die or even in the same die. In other words, each transistor in a die or wafer is different. The transistor parameter variations may be due to several factors, including changes in dielectric thickness, substrate, polysilicon, and implant impurity levels; surface charge; and lithographic process. Thus, the design decisions based on the nominal models may not be correct because the models are either overestimations or underestimations of actual values; hence, the resultant circuits may not be optimal. Accurate modelling and estimation of all the forms of power and performance accounting process variation, including all leakage components, are crucial for making correct decisions on design for manufacturing. Unfortunately, no comprehensive model or tools exist for accurate estimation during digital system design when the target technology is nanoscale CMOS. Some forms of the power dissipation, such as due to gate-oxide/junction tunneling, have not received much attention. Process-variation-aware modelling of any of the (leakage) current components or delay is significantly challenging when treated at system level. Moreover, no tool exists that can provide power-performance design space exploration when a system is a behavioural hardware description language (HDL). The research proposed in this project intends to develop process variation aware architectural power-delay statistical models and estimator that can be used for fast and accurate estimation of power-performance values of nanoscale-CMOS design alternatives of digital systems expressed as a behavioural HDL.