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A bidirectional power/data transfer platform based on electro-optical effects in standard CMOS

基于标准 CMOS 电光效应的双向电源/数据传输平台

基本信息

批准号：
EP/G070466/1
负责人：
Timothy Constandinou
金额：
$ 19.52万
依托单位：
Imperial College London
依托单位国家：
英国
项目类别：
Research Grant
财政年份：
2009
资助国家：
英国
起止时间：
2009 至无数据
项目状态：
已结题

来源：
https://gtr.ukri.org/projects?ref=EP%2FG070466%2F1
关键词：
bidirectional power data transfer platform

项目摘要

With the recent surge in the demand for lab-on-chip applications, the requirement for a low-cost integration of different technologies, in particular CMOS/MEMS and microfluidics has become crucial. Economies-of-scale especially driven by the semiconductor industry favour solutions based on unmodified commercial processes. The constraints dictated by the varying range of physical dimensions of the different components make wafer-level integration too costly for low-cost mass manufacture. For example, a typical lab-on-chip application may require CMOS components of area in the region of 1-10 sq. mm, MEMS components in the region of 25-100 sq. mm and microfluidics components in the region of 200-2500 sq. mm. Therefore integrating these at wafer level would be hugely wasteful to CMOS/MEMS technologies, as the common lab-on-chip area would be constrained by the requirement of interfacing fluids and external systems to the devices. A common technique for integrating these components at die-level, for example in chemical sensing, includes the following sequence. Wire bonding the chip to a package or substrate, encapsulating the wire bonds in an insulating material, levelling off the top surface, patterning the sensing regions (on chip surface) through the encapsulant, and finally aligning and laying on the microfluidics layers. The main challenges to this approach are all related to the fact that the bond wires are protruding above the sensing surface. In addition to this resulting in crucial reliability issues, the surface geometry is vastly affected, i.e. unwanted wells are created inside the bond pad regions and, the top surface (above the encapsulant) is far from planar- resulting in sealing and thus reliability issues when overlaying the microfluidics. A novel solution to this integration problem is proposed here. The idea is to develop a methodology for interfacing to CMOS chips without any bond wires such that the top chip surface is left planar with no bondpad openings. The challenge is therefore to develop a technique to: (1) provide power and control signals to a CMOS chip and (2) communicate data from the CMOS chip to an external device in a contactless fashion. Furthermore, an added challenge of having no off-chip connections is that no off-chip components, for example, antennas or capacitors can be used- such as in the case of RFID's. We therefore propose to apply optical techniques in a hybrid PCB/CMOS assembly such that the top surface is left virtually planar with all external components being mounted underneath the CMOS die. The scheme intends to supply power and control via an infrared (IR) emitter through the silicon using a relatively large area deep well photodiode to recover power and data. The transmitted light (i.e. non-absorbed photons) can therefore be modulated using electro-optical effects and reflected back through the die to a detector mounted beneath the CMOS die. The data can therefore be extracted from the received signal using relatively simple discrete electronics. Although this scheme is initially intended for hybrid, lab-on-chip applications, the wider scope for exploitation is enormous, with an impacting application-base throughout the microelectronics industry.

随着最近对芯片实验室应用的需求激增，对不同技术（特别是CMOS/MEMS和微流体）的低成本集成的需求变得至关重要。特别是半导体行业推动的规模经济有利于基于未经修改的商业流程的解决方案。由不同部件的物理尺寸的变化范围所决定的约束使得晶片级集成对于低成本大规模制造来说成本太高。例如，典型的芯片上实验室应用可能需要面积在1-10平方米范围内的CMOS组件。25-100 sq. mm和微流体组件在200-2500 sq.因此，在晶片级集成这些对于CMOS/MEMS技术来说将是巨大的浪费，因为共同的芯片上实验室区域将受到将流体和外部系统接口到器件的要求的限制。用于在管芯级集成这些组件的常见技术（例如在化学感测中）包括以下顺序。将芯片引线键合到封装或衬底，将引线键合封装在绝缘材料中，使顶表面平整，通过封装剂图案化感测区域（在芯片表面上），最后对准并放置在微流体层上。这种方法的主要挑战都与键合线突出于感测表面的事实有关。除了这导致关键的可靠性问题之外，表面几何形状受到极大的影响，即，在接合焊盘区域内产生不想要的威尔斯，并且顶表面（在密封剂上方）远离平面-导致密封，并且因此在覆盖微流体时导致可靠性问题。这里提出了一种新的解决方案，这个集成问题。这个想法是开发一种方法，用于在没有任何键合线的情况下与CMOS芯片接口，使得顶部芯片表面保持平坦，没有键合焊盘开口。因此，挑战在于开发一种技术来：（1）向CMOS芯片提供功率和控制信号，以及（2）以非接触方式将数据从CMOS芯片传送到外部设备。此外，没有片外连接的额外挑战是不能使用片外组件，例如天线或电容器-例如在RFID的情况下。因此，我们建议在混合PCB/CMOS组件中应用光学技术，使得顶表面几乎与安装在CMOS管芯下方的所有外部元件保持平面。该方案旨在使用相对大面积的深井光电二极管通过硅经由红外（IR）发射器提供功率和控制以恢复功率和数据。因此，可以使用电光效应来调制透射光（即，未吸收的光子），并且透射光通过管芯反射回安装在CMOS管芯下方的检测器。因此，可以使用相对简单的分立电子器件从接收信号中提取数据。虽然这种方案最初是针对混合芯片实验室应用的，但更广泛的开发范围是巨大的，在整个微电子行业都有影响力的应用基础。