Optimization of Massively Parallel Stochastic Simulations

大规模并行随机模拟的优化

• 批准号: EP/H017119/1
• 负责人: Christos Bouganis
• 金额: $ 12.53万
• 依托单位: Imperial College London
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2010
• 资助国家: 英国
• 起止时间: 2010 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FH017119%2F1
• 关键词: Optimization; Massively; Parallel; Stochastic; Simulations

Non-traditional architectures have shown massive energy savings and a significant boost on the performance of many applications across a range of domains. In order these high gains to be achieved, efficient use of silicon should be performed when such algorithms are mapped onto hardware. Even though this topic is well researched for the case of deterministic algorithms, no work has been done for algorithms of a stochastic nature. The fundamental problem that this proposal addresses is the efficiently use of silicon when a stochastic algorithm is mapped to hardware.This proposal is concerned with the design automation of hardware architectures for Monte Carlo based simulations of Stochastic Differential Equations (SDEs). Domains such as the stochastic modelling of chemical reactions and financial engineering are two examples where SDEs are widely used. Due to the non-existence or to high complexity in deriving an analytic solution for an SDE, numerical techniques based on computationally heavy Monte Carlo simulations are often employed. Hardware systems based on reconfigurable logic have demonstrated good potential for the acceleration and power consumption reduction of the above simulations. The main technique that is often employed and contributes to the realization of high performance gains and significant power consumption reduction is the use of a customized number representation system.This project aims to investigate two key issues related to the use Field Programmable Gate Arrays, a reconfigurable hardware device, for acceleration of Monte Carlo simulations for Stochastic Differential Equations. The first issue is the impact of the employed number representation on the quality of the SDE solution using Monte Carlo simulations, while the second key issue is to research and develop hardware architectures and word-length optimization techniques that target the minimization of power usage or the maximization of the performance of the system, without significant loss on the quality of the solution. By optimizing the computational part of the hardware system, efficient allocation of the available resources is performed, resulting in the acceleration of the overall simulation and improved energy consumption per computational operation.

非传统架构已显示出巨大的节能效果，并显着提升了跨领域的许多应用程序的性能。为了实现这些高增益，当将此类算法映射到硬件上时，应该有效地利用硅。尽管该主题针对确定性算法的情况进行了深入研究，但尚未针对随机性质的算法进行任何工作。该提案解决的基本问题是当随机算法映射到硬件时如何有效地使用芯片。该提案涉及基于蒙特卡罗的随机微分方程 (SDE) 模拟的硬件架构的设计自动化。化学反应的随机建模和金融工程等领域是 SDE 广泛使用的两个例子。由于 SDE 的解析解不存在或推导过程非常复杂，因此经常采用基于计算量大的蒙特卡罗模拟的数值技术。基于可重构逻辑的硬件系统已经展示了上述模拟的加速和功耗降低的良好潜力。经常采用的、有助于实现高性能增益和显着降低功耗的主要技术是使用定制的数字表示系统。该项目旨在研究与使用现场可编程门阵列（一种可重新配置的硬件设备）相关的两个关键问题，以加速随机微分方程的蒙特卡罗模拟。第一个问题是所采用的数字表示对使用蒙特卡罗模拟的SDE解决方案质量的影响，而第二个关键问题是研究和开发硬件架构和字长优化技术，其目标是最小化功耗或最大化系统性能，而不会对解决方案的质量造成重大损失。通过优化硬件系统的计算部分，可以有效分配可用资源，从而加速整体模拟并改善每个计算操作的能耗。