Optimization of Massively Parallel Stochastic Simulations

非传统架构已显示出巨大的节能效果，并显著提升了一系列领域的许多应用程序的性能。为了实现这些高增益，当这样的算法被映射到硬件上时，应该执行硅的有效使用。尽管这一主题对于确定性算法的情况进行了很好的研究，但对于随机性质的算法还没有做过任何工作。该方案解决的基本问题是当随机算法被映射到硬件时硅的有效利用。该方案涉及基于蒙特卡罗的随机微分方程(SDE)模拟的硬件结构的设计自动化。化学反应的随机建模和金融工程等领域是SDE被广泛使用的两个例子。由于SDE的解析解不存在或计算复杂，通常采用基于计算量较大的蒙特卡罗模拟的数值方法。基于可重构逻辑的硬件系统在加速和降低功耗方面表现出了良好的潜力。使用定制的数字表示系统是实现高性能增益和显著降低功耗的主要技术。本项目旨在研究与使用现场可编程门阵列(一种可重构的硬件设备)加速随机微分方程蒙特卡罗模拟相关的两个关键问题。第一个问题是采用的数字表示对使用蒙特卡罗模拟的SDE解的质量的影响，第二个关键问题是研究和开发硬件结构和字长优化技术，其目标是最小化功耗或最大化系统的性能，而不会对解的质量造成重大损失。通过优化硬件系统的计算部分，有效地分配了可用的资源，从而加速了整体模拟并改善了每次计算操作的能量消耗。

Non-traditional architectures have shown massive energy savings and a significant boost on the performance of many applications across a range of domains. In order these high gains to be achieved, efficient use of silicon should be performed when such algorithms are mapped onto hardware. Even though this topic is well researched for the case of deterministic algorithms, no work has been done for algorithms of a stochastic nature. The fundamental problem that this proposal addresses is the efficiently use of silicon when a stochastic algorithm is mapped to hardware.This proposal is concerned with the design automation of hardware architectures for Monte Carlo based simulations of Stochastic Differential Equations (SDEs). Domains such as the stochastic modelling of chemical reactions and financial engineering are two examples where SDEs are widely used. Due to the non-existence or to high complexity in deriving an analytic solution for an SDE, numerical techniques based on computationally heavy Monte Carlo simulations are often employed. Hardware systems based on reconfigurable logic have demonstrated good potential for the acceleration and power consumption reduction of the above simulations. The main technique that is often employed and contributes to the realization of high performance gains and significant power consumption reduction is the use of a customized number representation system.This project aims to investigate two key issues related to the use Field Programmable Gate Arrays, a reconfigurable hardware device, for acceleration of Monte Carlo simulations for Stochastic Differential Equations. The first issue is the impact of the employed number representation on the quality of the SDE solution using Monte Carlo simulations, while the second key issue is to research and develop hardware architectures and word-length optimization techniques that target the minimization of power usage or the maximization of the performance of the system, without significant loss on the quality of the solution. By optimizing the computational part of the hardware system, efficient allocation of the available resources is performed, resulting in the acceleration of the overall simulation and improved energy consumption per computational operation.