Quantum Simulations of Future Solid State Transistors

电脑和电子产品，如iPhone，已经改变了现代生活。硅晶体管是这场革命的核心，在过去的40年里，它不断地被制造得更快、更小。在一个芯片中，数百万个开关被挤在一个针头大小的区域内，在一秒钟内切换10亿次。晶体管的尺寸现在已经达到了纳米尺度;一纳米只比一个原子大十倍。摩尔定律规定晶体管尺寸每两年减半，是电子行业成功的推动力，但该定律已陷入停滞。晶体管缩放的快乐和轻松的日子现在已经一去不复返了。量子力学定律与晶体管的功能背道而驰，使其在关闭时泄漏，并产生不良的电气控制。此外，我们无法在制造过程中控制界面的精确原子结构和化学成分，这使得晶体管的可预测性更低。因此，半导体公司正在寻找替代的非平面（多栅极）晶体管架构和新型器件，如纳米线，纳米管，石墨烯和分子晶体管，这些器件最终将突破纳米尺寸的障碍，从而进入一个全新的小型化时代。在我们制造晶体管的能力和预测它们的行为之间存在着巨大的差距，硅晶体管的模拟和预测已经成为一项至关重要的使命。当前平面晶体管架构在关于泄漏和可控性的可缩放性方面存在严重问题。纳米尺寸的晶体管比它们以前微米尺寸的表亲更容易受到物质原子性质的影响。此外，在纳米尺度下，由于热导率的降低，热传递是新型晶体管应用的热死亡的来源。在此背景下，我建议开发一个量子器件模拟器，具有原子分辨率，可以准确预测当前和未来的晶体管性能。模拟器将部署电子传播的量子波描述，在完全量子力学水平上处理电子与晶格振动（热）的相互作用。它将有能力描述电子与半导体/电介质界面的粗糙度的相互作用，并在高电场的影响下与彼此。设备将在材料、化学成分和几何形状方面进行适当的测试和优化，而不会产生制造中隐含的高成本。广泛的晶体管将探讨从平面，非平面和新颖的。这是及时的，因为现有的计算机设计工具缺乏纳米级的预测能力，工业构建和测试方法已经变得过于昂贵。有效的量子模型/算法/方法和工具将被开发出来。随着器件尺寸向原子领域靠拢，这是一个动态的时代，而原子本质上是不可控的。在这种制度下，两股潮流发生碰撞：经典世界和量子世界使得我们在这种规模上努力征服自然时对新的模式和模式的需求至关重要。这提供了现有的机会，合并工程自上而下的方法与物理自下而上的方法。随着21世纪世纪对环境问题的关注，对绿色技术的需求正在增加。我的提案涉及降低功耗、减少原材料以提供更多功能以及提供更便宜的方式来评估新设计技术。总的来说，这些将有助于公司为消费者提供更环保的替代品。

Computers and electronic gadgets, such as the iphone, have transformed modern life. The silicon transistor is at the core of this revolution, having been continuously made faster and smaller over the last forty years. In a chip, millions of them are squeezed into an area the size of a pinhead, switching a billion times in one second. Transistor size has now reached nanometre dimensions; one nanometre is only ten time larger than an atom. Moore's law, which dictates that transistor size halves every two years and is the driving force behind the success of the electronics industry, has come to a halt. The happy and easy days of transistor scaling are now gone. Quantum mechanical laws conspire against transistor function making it leak when switched off and generating poor electrical control. Also, our inability to control the precise atomic structure of interfaces and chemical composition during fabrication makes transistors less predictable. Hence semiconductor companies are searching for alternative, non-planar (multigate) transistor architectures and novel devices such as nanowires, nanotubes, graphene and molecular transistors, which will ultimately break through the nano-size barrier resulting in a completely new era of miniaturization. There is a significant gap between our ability to fabricate transistors and to predict their behaviour.The simulation and prediction of the silicon transistor has become an vital mission. Current planar transistor architecture presents serious problems in scalability regarding leakage and controllability. Transistors of nanometre dimensions are more vulnerable to the atomic nature of matter than their previous cousins of micrometre dimensions. Furthermore, at nanoscales heat transfer is a source of heat death for novel transistor applications due to the decrease of thermal conductivity. Within this context I propose to develop a Quantum Device simulator, with atomic resolution that will enable the accurate prediction of present and future transistor performance. The simulator will deploy a quantum wave description of electron propagation, treating the interaction of electrons with crystal lattice vibrations (heat) at a fully quantum mechanical level. It will have the capability of describing the electron interactions with the roughness of the semiconductor/dielectric interface and with each other under the effect of a high electric field. Devices will be properly tested and optimised regarding materials, chemical composition and geometry without the high costs implicit in fabrication. A wide range of transistors will be explored from planar, non-planar and novel. This is timely as existing computer design tools lack predictive capabilities at the nanoscale and the industrial build-and-test approach has become prohibitively costly. Efficient quantum-models/algorithms/methodologies and tools will be developed.These are dynamic times as device dimensions move closer to the realm of atoms, which are inherently uncontrollable. In this regime two streams collide: the classical and quantum worlds making the need for new regularities and patterns vital as we strive to conquer nature at this scale. This offers exiting opportunities to merge an engineering top-to-bottom approach with a physics bottom-up approach. As 21st century environmental concerns rise, the need for greener technology is increasing. My proposal addresses the lowering of power consumption, raw material reductions delivering more functionality and the provision of a cheaper way to assess new design technologies. Collectively, these will help companies to provide a greener alternative to consumers.