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Highly-parallel algorithms and architectures for high-throughput wireless receivers

高吞吐量无线接收器的高度并行算法和架构

基本信息

批准号：
EP/L010550/1
负责人：
Rob Maunder
金额：
$ 61.19万
依托单位：
University of Southampton
依托单位国家：
英国
项目类别：
Research Grant
财政年份：
2014
资助国家：
英国
起止时间：
2014 至无数据
项目状态：
已结题

来源：
https://gtr.ukri.org/projects?ref=EP%2FL010550%2F1
关键词：
Highly parallel algorithms architectures throughput

项目摘要

During the past two decades, reliable wireless communication at near-theoretical-limit transmission throughputs has been facilitated by receivers that operate on the basis of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. Most famously, this algorithm is employed for turbo error correction in the Long Term Evolution (LTE) standard for cellular telephony, as well as in its previous-generation predecessors. Looking forward, turbo error correction promises transmission throughputs in excess of 1 Gbit/s, which is the goal specified in the IMT-Advanced requirements for next-generation cellular telephony standards. Throughputs of this order have only very recently been achieved by State-Of-the-Art (SOA) LTE turbo decoder implementations. However, this has been achieved by exploiting every possible opportunity to increase the parallelism of the BCJR algorithm at an architectural level, implying that the SOA approach has reached its fundamental limit. This limit may be attributed to the data dependencies of the BCJR algorithm, resulting in an inherently serial nature that cannot be readily mapped to processing architectures having a high degree of parallelism.Against this background, we propose to redesign turbo decoder implementations at an algorithmic level, rather than at the architectural level of the SOA approach. More specifically, we have recently been successful in devising an alternative to the BCJR algorithm, which has the same error correction capability, but does not have any data dependencies. Owing to this, our algorithm can be mapped to highly-parallel many-core processing architectures, facilitating an LTE turbo decoder processing throughput that is more than an order of magnitude higher than the SOA, satisfying future demands for gigabit throughputs. We will achieve this for the first time by developing a custom Field Programmable Gate Array (FPGA) architecture, comprising hundreds of processing cores that are interconnected using a reconfigurable Benes network. Furthermore, we will develop custom Network-on-Chip (NoC) architectures that facilitate different trade-offs between chip area, energy-efficiency, reconfigurability, processing throughput and latency. In parallel to developing these high-performance custom implementation architectures, we will apply our novel algorithm to both existing Graphics Processing Unit (GPU) and NoC architectures. This will grant us a rapid pace, allowing us to apply our novel algorithm to not only error correction, but to all aspects of receiver operation, including demodulation, equalisation, source decoding, channel estimation and synchronisation. Drawing upon our high-throughput algorithms and highly-parallel processing architectures, we will develop techniques for holistically optimising the algorithmic and implementational parameters of both the transmitter and receiver. This will facilitate practical high-performance schemes, which can pave the way for future generations of wireless communication.This research addresses key EPSRC priorities in the Information and Communication Technologies theme (http://www.epsrc.ac.uk/ourportfolio/themes/ict), including 'Many-core architectures and concurrency in distributed and embedded systems' and 'Towards an intelligent information infrastructure'. The 'Working together' priority is also addressed, since this cross-disciplinary research will develop new knowledge that spans the gap between high-performance communication theory and high-performance hardware design. This research will offer new insights into the design of many-core architectures, which the hardware design community will be able to apply in the design of general purpose architectures. Furthermore, the communication theory community will be able to apply our algorithms across even wider aspects of receiver operation.

在过去的二十年中，在接近理论极限的传输吞吐量的可靠的无线通信已经由基于Bahl-Cocke-Jelinek-Raviv（BCJR）算法操作的接收器促进。最著名的是，该算法被用于蜂窝电话的长期演进（LTE）标准及其上一代前辈中的turbo纠错。展望未来，Turbo纠错承诺传输吞吐量超过1 Gbit/s，这是下一代蜂窝电话标准的高级IMT要求中规定的目标。这种顺序的压缩仅在最近才通过最新技术水平（SOA）LTE turbo解码器实现来实现。然而，这是通过利用每一个可能的机会在架构级别上增加BCJR算法的并行性来实现的，这意味着SOA方法已经达到了它的基本极限。这种限制可能是由于BCJR算法的数据依赖关系，导致在一个固有的串行性质，不能很容易地映射到具有高度的parallels.Against这种背景下，处理架构，我们建议重新设计涡轮解码器实现在算法层面，而不是在SOA方法的架构层面。更具体地说，我们最近已经成功地设计了一种替代BCJR算法，它具有相同的纠错能力，但没有任何数据依赖性。由于这一点，我们的算法可以映射到高度并行的众核处理架构，促进LTE turbo解码器处理吞吐量比SOA高出一个数量级以上，满足未来千兆吞吐量的需求。我们将通过开发定制的现场可编程门阵列（FPGA）架构首次实现这一目标，该架构包括数百个使用可重新配置的Benes网络互连的处理核心。此外，我们将开发定制的片上网络（NoC）架构，以促进芯片面积，能效，可重构性，处理吞吐量和延迟之间的不同权衡。在开发这些高性能自定义实现架构的同时，我们将把我们的新算法应用到现有的图形处理单元（GPU）和NoC架构中。这将使我们的步伐很快，使我们能够应用我们的新算法，不仅纠错，但接收机操作的各个方面，包括解调，均衡，源解码，信道估计和同步。利用我们的高吞吐量算法和高度并行处理架构，我们将开发技术，全面优化发射机和接收机的算法和实现参数。这将有助于实际的高性能计划，这可以铺平道路，为未来几代的无线communication.This研究解决关键EPSRC优先事项的信息和通信技术的主题（http：//www.epsrc.ac.uk/ourportfolio/themes/ict），包括“多核架构和并发分布式和嵌入式系统”和“走向智能信息基础设施”。“共同努力”的优先事项也得到了解决，因为这种跨学科的研究将开发新的知识，跨越高性能通信理论和高性能硬件设计之间的差距差距。这项研究将为众核架构的设计提供新的见解，硬件设计社区将能够应用于通用架构的设计。此外，通信理论界将能够在接收机操作的更广泛方面应用我们的算法。