Highly-parallel algorithms and architectures for high-throughput wireless receivers

高吞吐量无线接收器的高度并行算法和架构

基本信息

批准号：
EP/L010550/1
负责人：
Rob Maunder
金额：
$ 61.19万
依托单位：
University of Southampton
依托单位国家：
英国
项目类别：
Research Grant
财政年份：
2014
资助国家：
英国
起止时间：
2014 至无数据
项目状态：
已结题

来源：
https://gtr.ukri.org/projects?ref=EP%2FL010550%2F1
关键词：
Highly parallel algorithms architectures throughput

项目摘要

During the past two decades, reliable wireless communication at near-theoretical-limit transmission throughputs has been facilitated by receivers that operate on the basis of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. Most famously, this algorithm is employed for turbo error correction in the Long Term Evolution (LTE) standard for cellular telephony, as well as in its previous-generation predecessors. Looking forward, turbo error correction promises transmission throughputs in excess of 1 Gbit/s, which is the goal specified in the IMT-Advanced requirements for next-generation cellular telephony standards. Throughputs of this order have only very recently been achieved by State-Of-the-Art (SOA) LTE turbo decoder implementations. However, this has been achieved by exploiting every possible opportunity to increase the parallelism of the BCJR algorithm at an architectural level, implying that the SOA approach has reached its fundamental limit. This limit may be attributed to the data dependencies of the BCJR algorithm, resulting in an inherently serial nature that cannot be readily mapped to processing architectures having a high degree of parallelism.Against this background, we propose to redesign turbo decoder implementations at an algorithmic level, rather than at the architectural level of the SOA approach. More specifically, we have recently been successful in devising an alternative to the BCJR algorithm, which has the same error correction capability, but does not have any data dependencies. Owing to this, our algorithm can be mapped to highly-parallel many-core processing architectures, facilitating an LTE turbo decoder processing throughput that is more than an order of magnitude higher than the SOA, satisfying future demands for gigabit throughputs. We will achieve this for the first time by developing a custom Field Programmable Gate Array (FPGA) architecture, comprising hundreds of processing cores that are interconnected using a reconfigurable Benes network. Furthermore, we will develop custom Network-on-Chip (NoC) architectures that facilitate different trade-offs between chip area, energy-efficiency, reconfigurability, processing throughput and latency. In parallel to developing these high-performance custom implementation architectures, we will apply our novel algorithm to both existing Graphics Processing Unit (GPU) and NoC architectures. This will grant us a rapid pace, allowing us to apply our novel algorithm to not only error correction, but to all aspects of receiver operation, including demodulation, equalisation, source decoding, channel estimation and synchronisation. Drawing upon our high-throughput algorithms and highly-parallel processing architectures, we will develop techniques for holistically optimising the algorithmic and implementational parameters of both the transmitter and receiver. This will facilitate practical high-performance schemes, which can pave the way for future generations of wireless communication.This research addresses key EPSRC priorities in the Information and Communication Technologies theme (http://www.epsrc.ac.uk/ourportfolio/themes/ict), including 'Many-core architectures and concurrency in distributed and embedded systems' and 'Towards an intelligent information infrastructure'. The 'Working together' priority is also addressed, since this cross-disciplinary research will develop new knowledge that spans the gap between high-performance communication theory and high-performance hardware design. This research will offer new insights into the design of many-core architectures, which the hardware design community will be able to apply in the design of general purpose architectures. Furthermore, the communication theory community will be able to apply our algorithms across even wider aspects of receiver operation.

在过去的二十年中，根据Bahl-Cocke-Jelinek-Raviv（BCJR）算法运行的接收器，已促进了可靠的无线通信。最著名的是，该算法用于长期演变（LTE）的蜂窝电话标准以及其前期的前身。展望未来，Turbo误差校正承诺传输吞吐量超过1 Gbit/s，这是下一代蜂窝电话标准的IMT先进要求中指定的目标。最新的（SOA）LTE Turbo解码器实施实现了该订单的吞吐量。但是，这是通过利用所有可能的机会来增加建筑层面BCJR算法的并行性来实现的，这意味着SOA方法已达到其基本限制。该限制可能归因于BCJR算法的数据依赖性，从而产生了固有的序列性质，无法容易地映射到具有高度并行性的架构。我们建议在算法层面上，而不是在SOAA ARCEADERARE级别上重新设计Turbo turbo解码器的实现。更具体地说，我们最近成功地设计了BCJR算法的替代方案，该算法具有相同的误差校正能力，但没有任何数据依赖性。因此，我们的算法可以映射到高度并行的多核处理体系结构，从而促进了LTE涡轮解码器处理吞吐量，该吞吐量远远超过SOA的数量级，满足了对千兆位吞吐量的未来需求。我们将首次通过开发自定义字段可编程栅极阵列（FPGA）体系结构来实现这一目标，其中包括数百个使用可重新配置的Benes网络互连的处理核心。此外，我们将开发自定义的网络芯片（NOC）体系结构，以促进芯片区域之间的不同权衡，能源效率，可重构性，处理吞吐量和延迟。在开发这些高性能自定义实现体系结构的同时，我们将应用新颖的算法将其应用于现有的图形处理单元（GPU）和NOC体系结构。这将使我们有一个快速的速度，使我们能够将新颖的算法应用于误差校正，还可以应用于接收器操作的各个方面，包括解调，均衡，源解码，通道估计和同步。利用我们的高通量算法和高度并行的处理体系结构，我们将开发用于整体优化发射器和接收器的算法和实现参数的技术。这将有助于实用的高性能方案，这可以为未来的几代无线通信铺平道路。这项研究涉及信息和通信技术主题（http://wwwwwwwwwwwwww.epsrc.ac.ac.uk/ourportfolio/themes/themes/ct-）的关键EPSRC优先级，包括“许多core”和“多个仪式”，并符合'许多core and and and and offerty and conforty and corment and'''''''''''''''''''''''''''''''和collenty'''''''和collenty式设施。基础设施'。还解决了“共同努力”的优先级，因为这项跨学科研究将开发新的知识，从而跨越高性能通信理论和高性能硬件设计之间的差距。这项研究将为多核体系结构的设计提供新的见解，硬件设计社区将能够应用于通用体系结构的设计。此外，传播理论社区将能够在接收器操作的更广泛方面应用我们的算法。