SCARV: a side-channel hardened RISC-V platform

RISC-V是一种指令集架构（伊萨）设计。伊萨本质上是任何兼容处理器实现应该能够执行的指令的规范，以及这些指令可以访问的资源;它充当处理器实现（硬件）和在其上执行的程序（软件）之间的接口。与Intel的x86伊萨等专有类似物形成鲜明对比的是，RISC-V是一种开源设计。这意味着任何人都可以出于任何目的免费使用它，这在一定程度上意味着围绕该项目快速开发了丰富的支持基础设施：这包括a）围绕相关非营利基金会构建的充满活力的开发人员和用户社区，B）伊萨的众多实现，无论是HDL（即，在FPGA平台上使用的软核）和硅（即，物理IC），以及c）编程工具链的端口（例如，GCC和LLVM）和操作系统（例如，类似的开放性是安全关键环境中的核心原则，与通常通俗地称为“模糊安全”的替代方案形成对比。在密码学领域尤其如此，这种技术通常负责确保我们数据（通信或存储）的保密性，鲁棒性和出处，以及我们与之交互的各方的真实性：加密标准，设计和实现的开放开发是现代规范。因此，RISC-V在用于执行加密软件时提供了各种机会。拟议的研究目标利用这些机会，以一种旨在解决对我们的数字安全乃至社会的高级、持续威胁的方式。具体而言：1）由于RISC-V可以由任何人实现，因此可以开发针对特定类型攻击的核心;重点将放在侧信道攻击的威胁上（这与嵌入式用例特别相关，例如，物联网）。除了这样做，拟议的研究将调查如何利用有关实现的详细信息来产生更有效的安全评估。2）由于RISC-V可以被任何人改编，因此可以开发各种特定于加密的伊萨扩展或变体，例如，提供更高的效率。如果加密软件更有效，它也可以更安全，因为，例如，可以部署更大的密钥或更强大的攻击对策，而不会对延迟产生显著影响。3）侧信道安全性的评估可能是禁止的，因为它需要各种特定的设备。利用基于RISC-V的平台，拟议的研究通过提供一个“实验室”来解决这个问题。自由”（即，基于云的）采集和分析工作流程。

RISC-V is an Instruction Set Architecture (ISA) design. An ISA is essentially a specification for the instructions any compatible processor implementation should be able to execute, and the resources those instructions can access; it acts as the interface between the processor implementation (hardware) and programs that execute on it (software). In sharp contrast with proprietary analogues such as the x86 ISA from Intel, RISC-V is an open source design. This means it can be used freely by anyone for any purpose, which, in part, has meant rapid development of a rich support infrastructure around the project: this includes a) vibrant developer and user communities, built around an associated non-profit foundation, b) numerous implementations of the ISA, both in HDL (i.e., a soft core for use on an FPGA platform) and silicon (i.e., physical ICs), and c) ports of programming tool-chains (e.g., GCC and LLVM) and operating systems (e.g., Linux).Similar openness is a core principle in security-critical contexts, contrasting with the alternative often colloquially termed "security by obscurity". This is particularly true in the field of cryptography, a technology routinely tasked with ensuring secrecy, robustness and provenience of our data (communicated or stored), and the authenticity of parties we interact with: open development of cryptographic standards, designs, and implementations is the modern norm. As a result, RISC-V presents various opportunities when used to execute cryptographic software. The proposed research goals capitalise on these opportunities, in a way designed to address advanced, persistent threats to our digital security, and, by extension, society. Specifically:1) Since RISC-V can be implemented by anyone, it is possible to develop a core hardened against specific types of attack; the focus will be on the threat of side-channel attacks (which is particularly relevant to embedded use-cases, e.g., IoT). As well as doing so, the proposed research will investigation how detailed information about the implementation can be harnessed to produce more effective security evaluations.2) Since RISC-V can be adapted by anyone, it is possible to develop various cryptography-specific extensions or variants of the ISA that offer either, for example, higher efficiency. If cryptographic software is more efficient it can also be more secure, because, for example, larger keys or more robust attack countermeasures can be deployed without as significant an impact on latency.3) Evaluation of side-channel security can be prohibitive in the sense it needs various specific items of equipment. Harnessing a platform based on RISC-V, the proposed research with address this problem by offering a "lab. free" (i.e., cloud-based) acquisition and analysis workflow available to anyone.