Innovative parallelism and programming for micro-core architectures

点击翻译按钮获取中文摘要

Modern central processing units (CPU) have provided significant performance gains over previous generations but at increasingly unsustainable levels of power consumption. Micro-core architectures combine a large number of simple, low-power, low-memory cores placed on a single chip, providing significant parallel performance at very low power levels. However, micro-core architectures are difficult to program and the immaturity of programming support is currently a significant barrier to adoption.This research centres around the hypothesis that non-HPC programmers find parallelisation techniques found in micro-core architectures difficult and their preferred choice of dynamic programming languages (e.g. Python) exacerbates the issue. The focus of this work is concerned with programmability, both in terms of design and implementation. The programming language ePython has been used as a research vehicle for the work, with the intention that findings from the research questions will have a wide relevance to mainstream technologies.The research questions that this project is currently addressing are:1. What is the most effective way to support programmer interaction with micro-core architectures?2. Are the techniques in the current ePython implementation appropriate for other micro-core architectures?3. What is the realistic performance that Python / High-Level Language programmers can expect on micro-core architectures?ePython has been developed specifically to target micro-core architectures, providing a simple, yet rich, parallel programming environment. It has been successfully ported to a number of micro-core architectures: the Adapteva Epiphany III, Xilinx MicroBlaze and PicoRV32 RISC-V.This work has resulted in two key achievements for the leveraging of extremely memory-constrained micro-core accelerators within the ePython programming language: the ability to manage arbitrary large data and the support of natively compiled codes of unbounded size. ePython now not only provides Python developers with performance approaching 90% of hand-coded C applications with dynamic code loading, within a minimum memory footprint of only 3KB.The restrictions imposed by the COVID-19 pandemic have had, and continue to have, a major impact on my family care duties and household income, requiring additional non-project work. Consequently, an application was submitted and granted for a 6-month EPSRC PhD funding extension, ensuring that the project will be successfully brought back on track.Publications:M. Jamieson and N. Brown, 'High level programming abstractions for leveraging hierarchical memories with micro-core architectures', Journal of Parallel and Distributed Computing, vol. 138, pp. 128-138, Apr. 2020, doi: 10.1016/j.jpdc.2019.11.011.M. Jamieson, N. Brown, and S. Liu, 'Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro-core architectures using ePython', Proceedings of the 19th Python in Science Conference (SciPy2020), Virtual Conference, pp. 107-115, 2020, doi: 10.25080/Majora-342d178e-00f.Conference posters:M. Jamieson, N. Brown, 'Eithne: A Framework for Benchmarking Micro-Core Accelerators', Poster presented at: SC19 Conference, Denver, Colorado, 2019 Nov 17-22. [Online]. Available: https://sc19.supercomputing.org/proceedings/tech_poster/tech_poster_pages/rpost186.htmlM. Jamieson, N. Brown, and S. Liu, 'Having your Cake and Eating it: Exploiting Python for Programmer Productivity and Performance on Micro-core Architectures Using ePython', Poster presented at: 19th Python in Science Conference (SciPy2020), Virtual Conference, 2020 Jul 6-12. [Online]. Available: https://raw.githubusercontent.com/mesham/epython/master/docs/SciPy-20-landscape-v1d6.pdf