Innovative parallelism and programming for micro-core architectures

与前几代产品相比，现代中央处理器(CPU)提供了显著的性能提升，但功耗水平越来越不可持续。微核架构将大量放置在单个芯片上的简单、低功耗、低内存的内核结合在一起，在非常低的功耗水平下提供显著的并行性能。然而，微核体系结构很难编程，编程支持的不成熟是目前采用的一个重要障碍。这项研究围绕这样一个假设：非HPC程序员发现微核体系结构中的并行化技术很难实现，他们首选的动态编程语言(如Python)加剧了这一问题。这项工作的重点是在设计和实现方面的可编程性。本项目目前正在解决的研究问题是：1.支持程序员与微核体系结构交互的最有效方式是什么？2.当前ePython实现中的技术是否适用于其他微核体系结构？3.Python/高级语言程序员在微核体系结构上期望的实际性能是什么？ePython是专门针对微核体系结构开发的，提供了一个简单而丰富的并行编程环境。它已经被成功地移植到许多微核架构上：Adapteva Epiphany III、Xilinx MicroBlaze和PicoRV32 RISC-V。这项工作为在ePython编程语言中利用内存极其有限的微核加速器带来了两个关键成就：管理任意大型数据的能力和对无限大小的本地编译代码的支持。EPython现在不仅为Python语言开发人员提供了接近90%的手工编写的C应用程序的动态代码加载性能，而且最低内存使用量仅为3KB。新冠肺炎疫情施加的限制已经并将继续对我的家庭护理职责和家庭收入产生重大影响，需要额外的非项目工作。因此，提交并批准了为期6个月的EPSRC博士资金延期申请，确保该项目将成功地重回正轨。出版物：M.Jamieson和N.Brown，《利用具有微核心架构的分层存储器的高级编程抽象》，《并行和分布式计算杂志》，第138卷，第128-138页，2020年4月，DOI：10.1016/j.jpdc.2019.11.011.M.Jamieson，N.Brown，和S.Liu，《拿着你的蛋糕吃：利用Python在微核架构上提高程序员的生产力和性能》，第19届巨蟒科学会议论文集(SciPy2020)，虚拟会议，第107-115页，2020年，DOI：10.25080/Majora-342d178e-00f。会议海报：M.Jamieson，N.Brown，‘Eithne：A Framechmark for Benchmark Micro-Core Accelerator’，海报提交于：SC19 Conference，丹佛，科罗拉多州，2019年11月17-22日。[在线]。提供：https://sc19.supercomputing.org/proceedings/tech_poster/tech_poster_pages/rpost186.htmlM.Jamieson，N.Brown，and S.Liu，《有你的蛋糕和吃它：利用Python提高程序员的生产力和使用ePython在微核架构上的性能》，海报提交于：第19届Python in Science Conference(SciPy2020)，虚拟会议，2020年7月6-12日。[在线]。提供：https://raw.githubusercontent.com/mesham/epython/master/docs/SciPy-20-landscape-v1d6.pdf

Modern central processing units (CPU) have provided significant performance gains over previous generations but at increasingly unsustainable levels of power consumption. Micro-core architectures combine a large number of simple, low-power, low-memory cores placed on a single chip, providing significant parallel performance at very low power levels. However, micro-core architectures are difficult to program and the immaturity of programming support is currently a significant barrier to adoption.This research centres around the hypothesis that non-HPC programmers find parallelisation techniques found in micro-core architectures difficult and their preferred choice of dynamic programming languages (e.g. Python) exacerbates the issue. The focus of this work is concerned with programmability, both in terms of design and implementation. The programming language ePython has been used as a research vehicle for the work, with the intention that findings from the research questions will have a wide relevance to mainstream technologies.The research questions that this project is currently addressing are:1. What is the most effective way to support programmer interaction with micro-core architectures?2. Are the techniques in the current ePython implementation appropriate for other micro-core architectures?3. What is the realistic performance that Python / High-Level Language programmers can expect on micro-core architectures?ePython has been developed specifically to target micro-core architectures, providing a simple, yet rich, parallel programming environment. It has been successfully ported to a number of micro-core architectures: the Adapteva Epiphany III, Xilinx MicroBlaze and PicoRV32 RISC-V.This work has resulted in two key achievements for the leveraging of extremely memory-constrained micro-core accelerators within the ePython programming language: the ability to manage arbitrary large data and the support of natively compiled codes of unbounded size. ePython now not only provides Python developers with performance approaching 90% of hand-coded C applications with dynamic code loading, within a minimum memory footprint of only 3KB.The restrictions imposed by the COVID-19 pandemic have had, and continue to have, a major impact on my family care duties and household income, requiring additional non-project work. Consequently, an application was submitted and granted for a 6-month EPSRC PhD funding extension, ensuring that the project will be successfully brought back on track.Publications:M. Jamieson and N. Brown, 'High level programming abstractions for leveraging hierarchical memories with micro-core architectures', Journal of Parallel and Distributed Computing, vol. 138, pp. 128-138, Apr. 2020, doi: 10.1016/j.jpdc.2019.11.011.M. Jamieson, N. Brown, and S. Liu, 'Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro-core architectures using ePython', Proceedings of the 19th Python in Science Conference (SciPy2020), Virtual Conference, pp. 107-115, 2020, doi: 10.25080/Majora-342d178e-00f.Conference posters:M. Jamieson, N. Brown, 'Eithne: A Framework for Benchmarking Micro-Core Accelerators', Poster presented at: SC19 Conference, Denver, Colorado, 2019 Nov 17-22. [Online]. Available: https://sc19.supercomputing.org/proceedings/tech_poster/tech_poster_pages/rpost186.htmlM. Jamieson, N. Brown, and S. Liu, 'Having your Cake and Eating it: Exploiting Python for Programmer Productivity and Performance on Micro-core Architectures Using ePython', Poster presented at: 19th Python in Science Conference (SciPy2020), Virtual Conference, 2020 Jul 6-12. [Online]. Available: https://raw.githubusercontent.com/mesham/epython/master/docs/SciPy-20-landscape-v1d6.pdf