Workshop on High-Level Programming Models for Parallelism

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The past decade has witnessed a sea change in the way that computing systems are designed, programmed, implemented, and evaluated. The advent of multicore technologies has fundamentally reshaped the long-standing contract between hardware and software - no longer can we simply rely on improvements in clock speeds to have our programs run faster. Instead, the burden for improvements in program performance now falls squarely on software and algorithms. Devising new techniques to efficiently and safely exploit multiple cores is the central question facing language designers, compiler writers, and system architects.To help address these challenges, this NSF sponsored workshop will identify future research directions related to High-Level Programming Models for Parallelism, and the transition of such research to industrial practice. The workshop will bring together researchers from academia, industry, and government research labs working in the area of parallelism, including algorithms, architecture, language design and implementation, and runtime systems. The workshop will identify primary challenges in the field, both foundational and infrastructural, and will address the transition of ideas from research to practice.